diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index d7ab29ed5224..a41dee385f8e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1041,7 +1041,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) { - u32 tmp = intel_de_read(dev_priv, DBUF_CTL); + u32 tmp = intel_de_read(dev_priv, DBUF_CTL_S(0)); WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != (DBUF_POWER_STATE | DBUF_POWER_REQUEST), @@ -4425,12 +4425,12 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) { - intel_dbuf_slice_set(dev_priv, DBUF_CTL, true); + intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), true); } static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) { - intel_dbuf_slice_set(dev_priv, DBUF_CTL, false); + intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), false); } static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) @@ -4456,9 +4456,11 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, return; if (req_slices > hw_enabled_slices) - ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); + ret = intel_dbuf_slice_set(dev_priv, + DBUF_CTL_S(DBUF_S2), true); else - ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false); + ret = intel_dbuf_slice_set(dev_priv, + DBUF_CTL_S(DBUF_S2), false); if (ret) dev_priv->enabled_dbuf_slices_num = req_slices; @@ -4466,16 +4468,16 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, static void icl_dbuf_enable(struct drm_i915_private *dev_priv) { - intel_de_write(dev_priv, DBUF_CTL_S1, - intel_de_read(dev_priv, DBUF_CTL_S1) | DBUF_POWER_REQUEST); - intel_de_write(dev_priv, DBUF_CTL_S2, - intel_de_read(dev_priv, DBUF_CTL_S2) | DBUF_POWER_REQUEST); - intel_de_posting_read(dev_priv, DBUF_CTL_S2); + intel_de_write(dev_priv, DBUF_CTL_S(0), + intel_de_read(dev_priv, DBUF_CTL_S(0)) | DBUF_POWER_REQUEST); + intel_de_write(dev_priv, DBUF_CTL_S(1), + intel_de_read(dev_priv, DBUF_CTL_S(1)) | DBUF_POWER_REQUEST); + intel_de_posting_read(dev_priv, DBUF_CTL_S(1)); udelay(10); - if (!(intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) || - !(intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE)) + if (!(intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) || + !(intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE)) drm_err(&dev_priv->drm, "DBuf power enable timeout\n"); else /* @@ -4487,16 +4489,16 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv) static void icl_dbuf_disable(struct drm_i915_private *dev_priv) { - intel_de_write(dev_priv, DBUF_CTL_S1, - intel_de_read(dev_priv, DBUF_CTL_S1) & ~DBUF_POWER_REQUEST); - intel_de_write(dev_priv, DBUF_CTL_S2, - intel_de_read(dev_priv, DBUF_CTL_S2) & ~DBUF_POWER_REQUEST); - intel_de_posting_read(dev_priv, DBUF_CTL_S2); + intel_de_write(dev_priv, DBUF_CTL_S(0), + intel_de_read(dev_priv, DBUF_CTL_S(0)) & ~DBUF_POWER_REQUEST); + intel_de_write(dev_priv, DBUF_CTL_S(1), + intel_de_read(dev_priv, DBUF_CTL_S(1)) & ~DBUF_POWER_REQUEST); + intel_de_posting_read(dev_priv, DBUF_CTL_S(1)); udelay(10); - if ((intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) || - (intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE)) + if ((intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) || + (intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE)) drm_err(&dev_priv->drm, "DBuf power disable timeout!\n"); else /* diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 2608a65af7fa..601e000ffd0d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -307,6 +307,11 @@ intel_display_power_put_async(struct drm_i915_private *i915, } #endif +enum dbuf_slice { + DBUF_S1, + DBUF_S2, +}; + #define with_intel_display_power(i915, domain, wf) \ for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index ab3da6e70734..fa411ee08a9d 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2886,7 +2886,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); - MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS); MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0bd431f6a011..dc206723f25e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7753,9 +7753,9 @@ enum { #define DISP_ARB_CTL2 _MMIO(0x45004) #define DISP_DATA_PARTITION_5_6 (1 << 6) #define DISP_IPC_ENABLE (1 << 3) -#define DBUF_CTL _MMIO(0x45008) -#define DBUF_CTL_S1 _MMIO(0x45008) -#define DBUF_CTL_S2 _MMIO(0x44FE8) +#define _DBUF_CTL_S1 0x45008 +#define _DBUF_CTL_S2 0x44FE8 +#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2)) #define DBUF_POWER_REQUEST (1 << 31) #define DBUF_POWER_STATE (1 << 30) #define GEN7_MSG_CTL _MMIO(0x45010) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89aa188c8cf5..f9e00ca61302 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3613,7 +3613,7 @@ u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) * only that 1 slice enabled until we have a proper way for on-demand * toggling of the second slice. */ - if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE) + if (0 && I915_READ(DBUF_CTL_S(DBUF_S2)) & DBUF_POWER_STATE) enabled_dbuf_slices_num++; return enabled_dbuf_slices_num;