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clk: socfpga: switch to GENMASK()
Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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4b5fb7dc90
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25d4d341d3
5 changed files with 4 additions and 5 deletions
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@ -39,7 +39,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
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div = socfpgaclk->fixed_div;
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div = socfpgaclk->fixed_div;
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else if (socfpgaclk->div_reg) {
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else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= div_mask(socfpgaclk->width);
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val &= GENMASK(socfpgaclk->width - 1, 0);
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div = (1 << val);
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div = (1 << val);
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}
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}
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@ -105,7 +105,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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div = socfpgaclk->fixed_div;
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div = socfpgaclk->fixed_div;
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else if (socfpgaclk->div_reg) {
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else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= div_mask(socfpgaclk->width);
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val &= GENMASK(socfpgaclk->width - 1, 0);
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/* Check for GPIO_DB_CLK by its offset */
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/* Check for GPIO_DB_CLK by its offset */
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if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
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if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
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div = val + 1;
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div = val + 1;
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@ -38,7 +38,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
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div = socfpgaclk->fixed_div;
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div = socfpgaclk->fixed_div;
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} else if (socfpgaclk->div_reg) {
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} else if (socfpgaclk->div_reg) {
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div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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div &= div_mask(socfpgaclk->width);
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div &= GENMASK(socfpgaclk->width - 1, 0);
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div += 1;
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div += 1;
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} else {
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} else {
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div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
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div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
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@ -35,7 +35,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
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} else {
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} else {
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if (socfpgaclk->div_reg) {
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if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= div_mask(socfpgaclk->width);
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val &= GENMASK(socfpgaclk->width - 1, 0);
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parent_rate /= (val + 1);
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parent_rate /= (val + 1);
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}
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}
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div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
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div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
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@ -26,7 +26,6 @@
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#define CLKMGR_PERPLL_SRC 0xAC
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#define CLKMGR_PERPLL_SRC 0xAC
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#define SOCFPGA_MAX_PARENTS 5
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#define SOCFPGA_MAX_PARENTS 5
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#define div_mask(width) ((1 << (width)) - 1)
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#define streq(a, b) (strcmp((a), (b)) == 0)
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#define streq(a, b) (strcmp((a), (b)) == 0)
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
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