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dmaengine: at_hdmac: Add support for memory to memory sg transfers
This patch adds support for memory to memory scatter-gather transfers. Changes from V1: * Fixed coding style of the multi-line comments. Changes from V2: * Added setup of 'desc->tx_width' that is needed to calculate the residue. Signed-off-by: Torsten Fleischer <torfl6749@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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26f7af37ee
commit
265567fbca
1 changed files with 164 additions and 11 deletions
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@ -65,6 +65,21 @@ static void atc_issue_pending(struct dma_chan *chan);
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/*----------------------------------------------------------------------*/
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static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst,
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size_t len)
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{
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unsigned int width;
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if (!((src | dst | len) & 3))
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width = 2;
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else if (!((src | dst | len) & 1))
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width = 1;
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else
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width = 0;
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return width;
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}
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static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
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{
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return list_first_entry(&atchan->active_list,
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@ -628,16 +643,10 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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* We can be a lot more clever here, but this should take care
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* of the most common optimization.
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*/
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if (!((src | dest | len) & 3)) {
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ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
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src_width = dst_width = 2;
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} else if (!((src | dest | len) & 1)) {
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ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
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src_width = dst_width = 1;
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} else {
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ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
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src_width = dst_width = 0;
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}
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src_width = dst_width = atc_get_xfer_width(src, dest, len);
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ctrla = ATC_SRC_WIDTH(src_width) |
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ATC_DST_WIDTH(dst_width);
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for (offset = 0; offset < len; offset += xfer_count << src_width) {
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xfer_count = min_t(size_t, (len - offset) >> src_width,
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@ -821,6 +830,144 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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return NULL;
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}
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/**
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* atc_prep_dma_sg - prepare memory to memory scather-gather operation
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* @chan: the channel to prepare operation on
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* @dst_sg: destination scatterlist
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* @dst_nents: number of destination scatterlist entries
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* @src_sg: source scatterlist
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* @src_nents: number of source scatterlist entries
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* @flags: tx descriptor status flags
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*/
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static struct dma_async_tx_descriptor *
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atc_prep_dma_sg(struct dma_chan *chan,
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struct scatterlist *dst_sg, unsigned int dst_nents,
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struct scatterlist *src_sg, unsigned int src_nents,
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unsigned long flags)
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{
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struct at_dma_chan *atchan = to_at_dma_chan(chan);
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struct at_desc *desc = NULL;
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struct at_desc *first = NULL;
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struct at_desc *prev = NULL;
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unsigned int src_width;
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unsigned int dst_width;
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size_t xfer_count;
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u32 ctrla;
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u32 ctrlb;
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size_t dst_len = 0, src_len = 0;
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dma_addr_t dst = 0, src = 0;
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size_t len = 0, total_len = 0;
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if (unlikely(dst_nents == 0 || src_nents == 0))
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return NULL;
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if (unlikely(dst_sg == NULL || src_sg == NULL))
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return NULL;
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ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
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| ATC_SRC_ADDR_MODE_INCR
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| ATC_DST_ADDR_MODE_INCR
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| ATC_FC_MEM2MEM;
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/*
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* loop until there is either no more source or no more destination
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* scatterlist entry
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*/
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while (true) {
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/* prepare the next transfer */
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if (dst_len == 0) {
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/* no more destination scatterlist entries */
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if (!dst_sg || !dst_nents)
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break;
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dst = sg_dma_address(dst_sg);
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dst_len = sg_dma_len(dst_sg);
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dst_sg = sg_next(dst_sg);
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dst_nents--;
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}
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if (src_len == 0) {
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/* no more source scatterlist entries */
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if (!src_sg || !src_nents)
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break;
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src = sg_dma_address(src_sg);
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src_len = sg_dma_len(src_sg);
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src_sg = sg_next(src_sg);
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src_nents--;
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}
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len = min_t(size_t, src_len, dst_len);
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if (len == 0)
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continue;
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/* take care for the alignment */
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src_width = dst_width = atc_get_xfer_width(src, dst, len);
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ctrla = ATC_SRC_WIDTH(src_width) |
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ATC_DST_WIDTH(dst_width);
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/*
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* The number of transfers to set up refer to the source width
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* that depends on the alignment.
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*/
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xfer_count = len >> src_width;
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if (xfer_count > ATC_BTSIZE_MAX) {
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xfer_count = ATC_BTSIZE_MAX;
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len = ATC_BTSIZE_MAX << src_width;
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}
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/* create the transfer */
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desc = atc_desc_get(atchan);
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if (!desc)
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goto err_desc_get;
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desc->lli.saddr = src;
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desc->lli.daddr = dst;
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desc->lli.ctrla = ctrla | xfer_count;
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desc->lli.ctrlb = ctrlb;
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desc->txd.cookie = 0;
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desc->len = len;
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/*
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* Although we only need the transfer width for the first and
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* the last descriptor, its easier to set it to all descriptors.
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*/
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desc->tx_width = src_width;
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atc_desc_chain(&first, &prev, desc);
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/* update the lengths and addresses for the next loop cycle */
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dst_len -= len;
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src_len -= len;
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dst += len;
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src += len;
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total_len += len;
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}
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/* First descriptor of the chain embedds additional information */
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first->txd.cookie = -EBUSY;
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first->total_len = total_len;
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/* set end-of-link to the last link descriptor of list*/
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set_desc_eol(desc);
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first->txd.flags = flags; /* client is in control of this ack */
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return &first->txd;
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err_desc_get:
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atc_desc_put(atchan, first);
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return NULL;
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}
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/**
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* atc_dma_cyclic_check_values
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* Check for too big/unaligned periods and unaligned DMA buffer
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@ -1421,8 +1568,10 @@ static int __init at_dma_probe(struct platform_device *pdev)
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/* setup platform data for each SoC */
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dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
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dma_cap_set(DMA_SG, at91sam9rl_config.cap_mask);
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dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
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dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
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dma_cap_set(DMA_SG, at91sam9g45_config.cap_mask);
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/* get DMA parameters from controller type */
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plat_dat = at_dma_get_driver_data(pdev);
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@ -1542,11 +1691,15 @@ static int __init at_dma_probe(struct platform_device *pdev)
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atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
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}
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if (dma_has_cap(DMA_SG, atdma->dma_common.cap_mask))
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atdma->dma_common.device_prep_dma_sg = atc_prep_dma_sg;
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dma_writel(atdma, EN, AT_DMA_ENABLE);
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dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
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dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n",
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dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
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dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
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dma_has_cap(DMA_SG, atdma->dma_common.cap_mask) ? "sg-cpy " : "",
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plat_dat->nr_channels);
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dma_async_device_register(&atdma->dma_common);
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