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KVM: arm/arm64: vgic-v2: Limit ITARGETSR bits to number of VCPUs
The GICv2 spec says in section 4.3.12 that a "CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI." Currently we allow the guest to write any value in there and it can read that back. Mask the written value with the proper CPU mask to be spec compliant. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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1 changed files with 2 additions and 1 deletions
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@ -129,6 +129,7 @@ static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
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unsigned long val)
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unsigned long val)
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{
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
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int i;
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int i;
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/* GICD_ITARGETSR[0-7] are read-only */
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/* GICD_ITARGETSR[0-7] are read-only */
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@ -141,7 +142,7 @@ static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
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spin_lock(&irq->irq_lock);
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spin_lock(&irq->irq_lock);
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irq->targets = (val >> (i * 8)) & 0xff;
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irq->targets = (val >> (i * 8)) & cpu_mask;
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target = irq->targets ? __ffs(irq->targets) : 0;
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target = irq->targets ? __ffs(irq->targets) : 0;
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irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
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irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
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