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drm/i915/fbc: Polish the skl+ FBC stride override handling
Polish the FBC stride override stuff: - just call it override_cfb_stride since it'll be used on more gens later - Use REG_BIT() & co. for the registers and give everything CHICKEN_ prefix since glk+ will have a different register for this - Use intel_de_rmw() for the RMW Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210702204603.596-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
parent
cd4891e4f7
commit
2670ff5c72
3 changed files with 19 additions and 17 deletions
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@ -306,14 +306,15 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
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/* Display WA #0529: skl, kbl, bxt. */
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if (DISPLAY_VER(dev_priv) == 9) {
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u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
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u32 val = 0;
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val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
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if (params->override_cfb_stride)
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val |= CHICKEN_FBC_STRIDE_OVERRIDE |
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CHICKEN_FBC_STRIDE(params->override_cfb_stride);
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if (params->gen9_wa_cfb_stride)
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val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
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intel_de_write(dev_priv, CHICKEN_MISC_4, val);
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intel_de_rmw(dev_priv, CHICKEN_MISC_4,
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CHICKEN_FBC_STRIDE_OVERRIDE |
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CHICKEN_FBC_STRIDE_MASK, val);
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}
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dpfc_ctl = 0;
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@ -749,7 +750,7 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
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fbc->compressed_fb.size * fbc->limit;
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}
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static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
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static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
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{
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struct intel_fbc *fbc = &dev_priv->fbc;
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struct intel_fbc_state_cache *cache = &fbc->state_cache;
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@ -761,11 +762,11 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
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return 0;
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}
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static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
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static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private *dev_priv)
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{
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struct intel_fbc *fbc = &dev_priv->fbc;
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return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
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return fbc->params.override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv);
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}
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static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
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@ -950,7 +951,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
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params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
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params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
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params->override_cfb_stride = cache->override_cfb_stride;
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params->plane_visible = cache->plane.visible;
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}
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@ -984,7 +985,7 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
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if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
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return false;
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if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
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if (params->override_cfb_stride != cache->override_cfb_stride)
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return false;
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return true;
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@ -1258,7 +1259,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
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if (fbc->crtc) {
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if (fbc->crtc != crtc ||
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(!intel_fbc_cfb_size_changed(dev_priv) &&
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!intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
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!intel_fbc_override_cfb_stride_changed(dev_priv)))
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goto out;
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__intel_fbc_disable(dev_priv);
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@ -1280,7 +1281,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
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goto out;
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}
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cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
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cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
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drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
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pipe_name(crtc->pipe));
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@ -454,7 +454,7 @@ struct intel_fbc {
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} fb;
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unsigned int fence_y_offset;
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u16 gen9_wa_cfb_stride;
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u16 override_cfb_stride;
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u16 interval;
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s8 fence_id;
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bool psr2_active;
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@ -481,7 +481,7 @@ struct intel_fbc {
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int cfb_size;
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unsigned int fence_y_offset;
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u16 gen9_wa_cfb_stride;
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u16 override_cfb_stride;
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u16 interval;
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s8 fence_id;
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bool plane_visible;
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@ -8176,8 +8176,9 @@ enum {
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#define GLK_CL0_PWR_DOWN (1 << 10)
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#define CHICKEN_MISC_4 _MMIO(0x4208c)
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#define FBC_STRIDE_OVERRIDE (1 << 13)
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#define FBC_STRIDE_MASK 0x1FFF
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#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
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#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
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#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
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#define _CHICKEN_PIPESL_1_A 0x420b0
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#define _CHICKEN_PIPESL_1_B 0x420b4
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