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clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
parent
9387bfd19b
commit
268aebaa24
7 changed files with 45 additions and 11 deletions
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@ -158,12 +158,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
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writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
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reg_data->div_core_shift) |
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HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
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HIWORD_UPDATE(reg_data->mux_core_alt,
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reg_data->mux_core_mask,
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reg_data->mux_core_shift),
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cpuclk->reg_base + reg_data->core_reg);
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} else {
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/* select alternate parent */
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writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
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cpuclk->reg_base + reg_data->core_reg);
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writel(HIWORD_UPDATE(reg_data->mux_core_alt,
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reg_data->mux_core_mask,
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reg_data->mux_core_shift),
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cpuclk->reg_base + reg_data->core_reg);
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}
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spin_unlock_irqrestore(cpuclk->lock, flags);
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@ -198,7 +202,9 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
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writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
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reg_data->div_core_shift) |
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HIWORD_UPDATE(0, 1, reg_data->mux_core_shift),
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HIWORD_UPDATE(reg_data->mux_core_main,
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reg_data->mux_core_mask,
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reg_data->mux_core_shift),
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cpuclk->reg_base + reg_data->core_reg);
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if (ndata->old_rate > ndata->new_rate)
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@ -252,7 +258,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.parent_names = &parent_names[0];
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init.parent_names = &parent_names[reg_data->mux_core_main];
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init.num_parents = 1;
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init.ops = &rockchip_cpuclk_ops;
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@ -270,10 +276,10 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
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cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
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cpuclk->hw.init = &init;
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cpuclk->alt_parent = __clk_lookup(parent_names[1]);
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cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
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if (!cpuclk->alt_parent) {
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pr_err("%s: could not lookup alternate parent\n",
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__func__);
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pr_err("%s: could not lookup alternate parent: (%d)\n",
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__func__, reg_data->mux_core_alt);
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ret = -EINVAL;
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goto free_cpuclk;
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}
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@ -285,10 +291,11 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
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goto free_cpuclk;
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}
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clk = __clk_lookup(parent_names[0]);
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clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
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if (!clk) {
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pr_err("%s: could not lookup parent clock %s\n",
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__func__, parent_names[0]);
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pr_err("%s: could not lookup parent clock: (%d) %s\n",
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__func__, reg_data->mux_core_main,
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parent_names[reg_data->mux_core_main]);
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ret = -EINVAL;
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goto free_alt_parent;
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}
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@ -113,7 +113,10 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
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.core_reg = RK2928_CLKSEL_CON(0),
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.div_core_shift = 0,
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.div_core_mask = 0x1f,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 7,
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.mux_core_mask = 0x1,
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};
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PNAME(mux_pll_p) = { "xin24m", "xin24m" };
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@ -155,7 +155,10 @@ static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
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.core_reg = RK2928_CLKSEL_CON(0),
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.div_core_shift = 0,
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.div_core_mask = 0x1f,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 8,
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.mux_core_mask = 0x1,
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};
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#define RK3188_DIV_ACLK_CORE_MASK 0x7
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@ -191,7 +194,10 @@ static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
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.core_reg = RK2928_CLKSEL_CON(0),
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.div_core_shift = 9,
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.div_core_mask = 0x1f,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 8,
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.mux_core_mask = 0x1,
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};
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PNAME(mux_pll_p) = { "xin24m", "xin32k" };
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@ -111,7 +111,10 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
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.core_reg = RK2928_CLKSEL_CON(0),
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.div_core_shift = 0,
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.div_core_mask = 0x1f,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 6,
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.mux_core_mask = 0x1,
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};
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PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
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@ -165,7 +165,10 @@ static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
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.core_reg = RK3288_CLKSEL_CON(0),
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.div_core_shift = 8,
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.div_core_mask = 0x1f,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 15,
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.mux_core_mask = 0x1,
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};
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PNAME(mux_pll_p) = { "xin24m", "xin32k" };
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@ -165,14 +165,20 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
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.core_reg = RK3368_CLKSEL_CON(0),
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.div_core_shift = 0,
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.div_core_mask = 0x1f,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 7,
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.mux_core_mask = 0x1,
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};
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static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
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.core_reg = RK3368_CLKSEL_CON(2),
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.div_core_shift = 0,
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.div_core_mask = 0x1f,
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.mux_core_shift = 7,
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.mux_core_mask = 0x1,
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};
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#define RK3368_DIV_ACLKM_MASK 0x1f
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@ -217,14 +217,20 @@ struct rockchip_cpuclk_rate_table {
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* @core_reg: register offset of the core settings register
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* @div_core_shift: core divider offset used to divide the pll value
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* @div_core_mask: core divider mask
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* @mux_core_alt: mux value to select alternate parent
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* @mux_core_main: mux value to select main parent of core
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* @mux_core_shift: offset of the core multiplexer
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* @mux_core_mask: core multiplexer mask
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*/
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struct rockchip_cpuclk_reg_data {
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int core_reg;
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u8 div_core_shift;
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u32 div_core_mask;
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int mux_core_reg;
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u8 mux_core_alt;
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u8 mux_core_main;
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u8 mux_core_shift;
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u32 mux_core_mask;
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};
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struct clk *rockchip_clk_register_cpuclk(const char *name,
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