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MIPS: Octeon: Update feature test functions for new chips and features.
cvmx.h was rearranged to fix include file ordering problems, but there is no change other than moving some definitions around. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2984/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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parent
412394d104
commit
26afc5e399
2 changed files with 126 additions and 30 deletions
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@ -31,6 +31,27 @@
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#include <linux/kernel.h>
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#include <linux/string.h>
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enum cvmx_mips_space {
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CVMX_MIPS_SPACE_XKSEG = 3LL,
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CVMX_MIPS_SPACE_XKPHYS = 2LL,
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CVMX_MIPS_SPACE_XSSEG = 1LL,
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CVMX_MIPS_SPACE_XUSEG = 0LL
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};
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/* These macros for use when using 32 bit pointers. */
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#define CVMX_MIPS32_SPACE_KSEG0 1l
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#define CVMX_ADD_SEG32(segment, add) \
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(((int32_t)segment << 31) | (int32_t)(add))
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#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
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/* These macros simplify the process of creating common IO addresses */
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#define CVMX_ADD_SEG(segment, add) \
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((((uint64_t)segment) << 62) | (add))
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#ifndef CVMX_ADD_IO_SEG
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#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
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#endif
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#include "cvmx-asm.h"
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#include "cvmx-packet.h"
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#include "cvmx-sysinfo.h"
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@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
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return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
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}
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enum cvmx_mips_space {
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CVMX_MIPS_SPACE_XKSEG = 3LL,
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CVMX_MIPS_SPACE_XKPHYS = 2LL,
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CVMX_MIPS_SPACE_XSSEG = 1LL,
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CVMX_MIPS_SPACE_XUSEG = 0LL
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};
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/* These macros for use when using 32 bit pointers. */
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#define CVMX_MIPS32_SPACE_KSEG0 1l
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#define CVMX_ADD_SEG32(segment, add) \
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(((int32_t)segment << 31) | (int32_t)(add))
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#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
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/* These macros simplify the process of creating common IO addresses */
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#define CVMX_ADD_SEG(segment, add) \
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((((uint64_t)segment) << 62) | (add))
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#ifndef CVMX_ADD_IO_SEG
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#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
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#endif
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/**
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* Convert a memory pointer (void*) into a hardware compatible
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* memory address (uint64_t). Octeon hardware widgets don't
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@ -31,8 +31,14 @@
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#ifndef __OCTEON_FEATURE_H__
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#define __OCTEON_FEATURE_H__
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#include <asm/octeon/cvmx-mio-defs.h>
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#include <asm/octeon/cvmx-rnm-defs.h>
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enum octeon_feature {
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/* CN68XX uses port kinds for packet interface */
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OCTEON_FEATURE_PKND,
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/* CN68XX has different fields in word0 - word2 */
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OCTEON_FEATURE_CN68XX_WQE,
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/*
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* Octeon models in the CN5XXX family and higher support
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* atomic add instructions to memory (saa/saad).
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@ -42,8 +48,13 @@ enum octeon_feature {
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OCTEON_FEATURE_ZIP,
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/* Does this Octeon support crypto acceleration using COP2? */
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OCTEON_FEATURE_CRYPTO,
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OCTEON_FEATURE_DORM_CRYPTO,
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/* Does this Octeon support PCI express? */
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OCTEON_FEATURE_PCIE,
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/* Does this Octeon support SRIOs */
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OCTEON_FEATURE_SRIO,
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/* Does this Octeon support Interlaken */
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OCTEON_FEATURE_ILK,
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/* Some Octeon models support internal memory for storing
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* cryptographic keys */
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OCTEON_FEATURE_KEY_MEMORY,
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@ -64,6 +75,15 @@ enum octeon_feature {
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/* Octeon MDIO block supports clause 45 transactions for 10
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* Gig support */
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OCTEON_FEATURE_MDIO_CLAUSE_45,
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/*
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* CN52XX and CN56XX used a block named NPEI for PCIe
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* access. Newer chips replaced this with SLI+DPI.
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*/
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OCTEON_FEATURE_NPEI,
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OCTEON_FEATURE_HFA,
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OCTEON_FEATURE_DFM,
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OCTEON_FEATURE_CIU2,
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OCTEON_MAX_FEATURE
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};
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static inline int cvmx_fuse_read(int fuse);
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@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature)
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return !cvmx_fuse_read(121);
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case OCTEON_FEATURE_CRYPTO:
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return !cvmx_fuse_read(90);
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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union cvmx_mio_fus_dat2 fus_2;
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fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
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if (fus_2.s.nocrypto || fus_2.s.nomul) {
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return 0;
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} else if (!fus_2.s.dorm_crypto) {
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return 1;
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} else {
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union cvmx_rnm_ctl_status st;
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st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
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return st.s.eer_val;
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}
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} else {
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return !cvmx_fuse_read(90);
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}
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case OCTEON_FEATURE_DORM_CRYPTO:
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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union cvmx_mio_fus_dat2 fus_2;
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fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
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return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
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} else {
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return 0;
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}
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case OCTEON_FEATURE_PCIE:
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case OCTEON_FEATURE_MGMT_PORT:
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case OCTEON_FEATURE_RAID:
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return OCTEON_IS_MODEL(OCTEON_CN56XX)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX);
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|| OCTEON_IS_MODEL(OCTEON_CN52XX)
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|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
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case OCTEON_FEATURE_SRIO:
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return OCTEON_IS_MODEL(OCTEON_CN63XX)
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|| OCTEON_IS_MODEL(OCTEON_CN66XX);
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case OCTEON_FEATURE_ILK:
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return (OCTEON_IS_MODEL(OCTEON_CN68XX));
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case OCTEON_FEATURE_KEY_MEMORY:
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return OCTEON_IS_MODEL(OCTEON_CN38XX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX)
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|| OCTEON_IS_MODEL(OCTEON_CN56XX)
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|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
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case OCTEON_FEATURE_LED_CONTROLLER:
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return OCTEON_IS_MODEL(OCTEON_CN38XX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX)
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|| OCTEON_IS_MODEL(OCTEON_CN56XX);
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case OCTEON_FEATURE_TRA:
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return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX));
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case OCTEON_FEATURE_MGMT_PORT:
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return OCTEON_IS_MODEL(OCTEON_CN56XX)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX)
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|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
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case OCTEON_FEATURE_RAID:
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return OCTEON_IS_MODEL(OCTEON_CN56XX)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX)
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|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
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case OCTEON_FEATURE_USB:
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return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX));
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case OCTEON_FEATURE_NO_WPTR:
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return (OCTEON_IS_MODEL(OCTEON_CN56XX)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX))
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&& !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
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&& !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
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|| OCTEON_IS_MODEL(OCTEON_CN52XX)
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|| OCTEON_IS_MODEL(OCTEON_CN6XXX))
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&& !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
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&& !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
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case OCTEON_FEATURE_DFA:
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if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
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&& !OCTEON_IS_MODEL(OCTEON_CN31XX)
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return 0;
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else if (OCTEON_IS_MODEL(OCTEON_CN3020))
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return 0;
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else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
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return 1;
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else
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return !cvmx_fuse_read(120);
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case OCTEON_FEATURE_HFA:
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if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
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return 0;
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else
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return !cvmx_fuse_read(90);
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case OCTEON_FEATURE_DFM:
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if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
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|| OCTEON_IS_MODEL(OCTEON_CN66XX)))
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return 0;
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else
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return !cvmx_fuse_read(90);
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case OCTEON_FEATURE_MDIO_CLAUSE_45:
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return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX));
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case OCTEON_FEATURE_NPEI:
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return OCTEON_IS_MODEL(OCTEON_CN56XX)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX);
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case OCTEON_FEATURE_PKND:
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return OCTEON_IS_MODEL(OCTEON_CN68XX);
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case OCTEON_FEATURE_CN68XX_WQE:
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return OCTEON_IS_MODEL(OCTEON_CN68XX);
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case OCTEON_FEATURE_CIU2:
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return OCTEON_IS_MODEL(OCTEON_CN68XX);
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default:
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break;
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}
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return 0;
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}
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