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[PATCH] ide: HPT3xx: fix PCI clock detection
Use the f_CNT value saved by the HighPoint BIOS if available as reading it directly would give us a wrong PCI frequency after DPLL has already been calibrated by BIOS. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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1 changed files with 32 additions and 14 deletions
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@ -70,6 +70,8 @@
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* - fix/remove bad/unused timing tables and use one set of tables for the whole
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* HPT37x chip family; save space by introducing the separate transfer mode
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* table in which the mode lookup is done
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* - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
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* the wrong PCI frequency since DPLL has already been calibrated by BIOS
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* - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
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* and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
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* - pass to init_chipset() handlers a copy of the IDE PCI device structure as
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@ -1010,8 +1012,8 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
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struct hpt_info *info = ide_get_hwifdata(hwif);
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struct pci_dev *dev = hwif->pci_dev;
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int adjust, i;
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u16 freq;
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u32 pll;
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u16 freq = 0;
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u32 pll, temp = 0;
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u8 reg5bh = 0, mcr1 = 0;
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/*
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@ -1025,15 +1027,34 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
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pci_write_config_byte(dev, 0x5b, 0x23);
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/*
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* set up the PLL. we need to adjust it so that it's stable.
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* freq = Tpll * 192 / Tpci
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* We'll have to read f_CNT value in order to determine
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* the PCI clock frequency according to the following ratio:
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*
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* Todo. For non x86 should probably check the dword is
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* set to 0xABCDExxx indicating the BIOS saved f_CNT
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* f_CNT = Fpci * 192 / Fdpll
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*
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* First try reading the register in which the HighPoint BIOS
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* saves f_CNT value before reprogramming the DPLL from its
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* default setting (which differs for the various chips).
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* In case the signature check fails, we'll have to resort to
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* reading the f_CNT register itself in hopes that nobody has
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* touched the DPLL yet...
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*/
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pci_read_config_word(dev, 0x78, &freq);
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freq &= 0x1FF;
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pci_read_config_dword(dev, 0x70, &temp);
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if ((temp & 0xFFFFF000) != 0xABCDE000) {
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int i;
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printk(KERN_WARNING "HPT37X: no clock data saved by BIOS\n");
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/* Calculate the average value of f_CNT */
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for (temp = i = 0; i < 128; i++) {
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pci_read_config_word(dev, 0x78, &freq);
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temp += freq & 0x1ff;
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mdelay(1);
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}
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freq = temp / 128;
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} else
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freq = temp & 0x1ff;
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/*
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* HPT3xxN chips use different PCI clock information.
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* Currently we always set up the PLL for them.
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@ -1095,11 +1116,8 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
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info->flags |= PLL_MODE;
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/*
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* FIXME: make this work correctly, esp with 372N as per
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* reference driver code.
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*
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* adjust PLL based upon PCI clock, enable it, and wait for
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* stabilization.
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* Adjust the PLL based upon the PCI clock, enable it, and
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* wait for stabilization...
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*/
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adjust = 0;
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freq = (pll < F_LOW_PCI_50) ? 2 : 4;
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