mvebu dt64 for 5.20 (part 1)
Add support for Marvell 98DX2530 (and variants) -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCYtavZAAKCRALBhiOFHI7 1cppAKCTWos36VwvV+vKWV0+DfOUcikV2QCdHLcmQ0ygjT6AsW2/yPJfoNuM4b0= =7i0h -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLWsuIACgkQmmx57+YA GNlY0xAAqm4ruRmNyoCpkGOjg72+SLJlEZbhELMarHLopKMYrM4fIxyruuGmD1Cp r1uv21oZiDJhmr1sXqbtjOghNdsce3s1tKrYoWeMFgFTfDQGu4Bw7NWZZgY5xeqI aGxCdFgD9pCYaZgIXYlEqC2qLQP1eGypSTCFjgw+7JWnq57hZxsBYuQnAJhlu79g +xpRUVoTEc7duPKE2m2Vb2FhoJVaLSMC5T0ZiqekGX3wAO4JEHwSa8YFLPJ04HGg DESXMiWVUPYWrZ86vce6rtn0JWCBRRGeI3rZxsRYQ3xWYMhq27CL3E5PkQcrNwIH 29gr/Uzu2d5JlJgMSyT8bk+79eHbvhQoX/Daossk3DvHCOfRjv3/POdYqfaoWGAd nq3W5oxW4X+8eXP/zY7p4o7i/y03j0/VtbgtCUEOk3OkL5idqQxXeJTnr1XSPdm4 NnAAhB1xTZ8o3v8ohMAIuNvdFbJ3Mq0o+xuYPRVSJwLPgnXfpQfWMdI9Ag4eK7MI 1wkV9g8SFwqvd/vZyI+6jYYo8FPkc0JYvs88cAMXy1Tjw6ywRKprUlBrM2My9tre Ta3b2W1JUHYrniQoet+Z0GKg5xOtjkS9K9n4P3/ilq8zNYCURSaJCGmdOLwQw4Zs ZB7/PFQcLRVMBEJ913RefxcJG5ShnOiwrLtYIsB1wI0SRn3VAMw= =FqlL -----END PGP SIGNATURE----- Merge tag 'mvebu-dt64-5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt mvebu dt64 for 5.20 (part 1) Add support for Marvell 98DX2530 (and variants) * tag 'mvebu-dt64-5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: marvell: enable the 98DX2530 pinctrl driver arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board dt-bindings: marvell: Document the AC5/AC5X compatibles Link: https://lore.kernel.org/r/87cze1qlg3.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
26c350fe7a
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@ -0,0 +1,32 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Alleycat5/5X Platforms
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maintainers:
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- Chris Packham <chris.packham@alliedtelesis.co.nz>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: Alleycat5 (98DX25xx) Reference Design
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items:
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- enum:
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- marvell,rd-ac5
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- const: marvell,ac5
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- description: Alleycat5X (98DX35xx) Reference Design
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items:
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- enum:
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- marvell,rd-ac5x
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- const: marvell,ac5x
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- const: marvell,ac5
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additionalProperties: true
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...
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@ -192,11 +192,13 @@ config ARCH_MVEBU
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select PINCTRL_ARMADA_37XX
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select PINCTRL_ARMADA_AP806
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select PINCTRL_ARMADA_CP110
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select PINCTRL_AC5
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help
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This enables support for Marvell EBU familly, including:
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- Armada 3700 SoC Family
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- Armada 7K SoC Family
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- Armada 8K SoC Family
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- 98DX2530 SoC Family
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config ARCH_MXC
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bool "ARMv8 based NXP i.MX SoC family"
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@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
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@ -0,0 +1,291 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree For AC5.
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*
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* Copyright (C) 2021 Marvell
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* Copyright (C) 2022 Allied Telesis Labs
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Marvell AC5 SoC";
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compatible = "marvell,ac5";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges;
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internal-regs@7f000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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/* 16M internal register @ 0x7f00_0000 */
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ranges = <0x0 0x0 0x7f000000 0x1000000>;
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dma-coherent;
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uart0: serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "okay";
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};
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mdio: mdio@22004 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x22004 0x4>;
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clocks = <&cnm_clock>;
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};
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i2c0: i2c@11000{
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compatible = "marvell,mv78230-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cnm_clock>;
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clock-names = "core";
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency=<100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-1 = <&i2c0_gpio>;
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scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
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sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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i2c1: i2c@11100{
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compatible = "marvell,mv78230-i2c";
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cnm_clock>;
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clock-names = "core";
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency=<100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-1 = <&i2c1_gpio>;
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scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl0 0 0 32>;
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marvell,pwm-offset = <0x1f0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio1: gpio@18140 {
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reg = <0x18140 0x40>;
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compatible = "marvell,orion-gpio";
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ngpios = <14>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl0 0 32 14>;
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marvell,pwm-offset = <0x1f0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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/*
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* Dedicated section for devices behind 32bit controllers so we
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* can configure specific DMA mapping for them
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*/
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behind-32bit-controller@7f000000 {
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compatible = "simple-bus";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
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/* Host phy ram starts at 0x200M */
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dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
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dma-coherent;
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eth0: ethernet@20000 {
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compatible = "marvell,armada-ac5-neta";
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reg = <0x0 0x20000 0x0 0x4000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cnm_clock>;
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phy-mode = "sgmii";
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status = "disabled";
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};
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eth1: ethernet@24000 {
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compatible = "marvell,armada-ac5-neta";
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reg = <0x0 0x24000 0x0 0x4000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cnm_clock>;
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phy-mode = "sgmii";
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status = "disabled";
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};
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usb0: usb@80000 {
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compatible = "marvell,orion-ehci";
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reg = <0x0 0x80000 0x0 0x500>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usb1: usb@a0000 {
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compatible = "marvell,orion-ehci";
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reg = <0x0 0xa0000 0x0 0x500>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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pinctrl0: pinctrl@80020100 {
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compatible = "marvell,ac5-pinctrl";
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reg = <0 0x80020100 0 0x20>;
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i2c0_pins: i2c0-pins {
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c0";
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};
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i2c0_gpio: i2c0-gpio-pins {
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "gpio";
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};
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i2c1_pins: i2c1-pins {
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marvell,pins = "mpp20", "mpp21";
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marvell,function = "i2c1";
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};
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i2c1_gpio: i2c1-gpio-pins {
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marvell,pins = "mpp20", "mpp21";
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marvell,function = "i2c1";
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};
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};
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spi0: spi@805a0000 {
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compatible = "marvell,armada-3700-spi";
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reg = <0x0 0x805a0000 0x0 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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clocks = <&spi_clock>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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status = "disabled";
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};
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|
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spi1: spi@805a8000 {
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compatible = "marvell,armada-3700-spi";
|
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reg = <0x0 0x805a8000 0x0 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
|
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clocks = <&spi_clock>;
|
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@80600000 {
|
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compatible = "arm,gic-v3";
|
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#interrupt-cells = <3>;
|
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interrupt-controller;
|
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reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
|
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<0x0 0x80660000 0x0 0x40000>; /* GICR */
|
||||
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
cnm_clock: cnm-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <328000000>;
|
||||
};
|
||||
|
||||
spi_clock: spi-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree For RD-AC5X.
|
||||
*
|
||||
* Copyright (C) 2021 Marvell
|
||||
* Copyright (C) 2022 Allied Telesis Labs
|
||||
*/
|
||||
/*
|
||||
* Device Tree file for Marvell Alleycat 5X development board
|
||||
* This board file supports the B configuration of the board
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ac5-98dx35xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell RD-AC5X Board";
|
||||
compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
spiflash0 = &spiflash0;
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x2 0x00000000 0x0 0x40000000>;
|
||||
};
|
||||
|
||||
usb1phy: usb-phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
/* USB0 is a host USB */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB1 is a peripheral USB */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
phys = <&usb1phy>;
|
||||
phy-names = "usb-phy";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spiflash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
|
||||
spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
|
||||
reg = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "spi_flash_part0";
|
||||
reg = <0x0 0x800000>;
|
||||
};
|
||||
|
||||
parition@1 {
|
||||
label = "spi_flash_part1";
|
||||
reg = <0x800000 0x700000>;
|
||||
};
|
||||
|
||||
parition@2 {
|
||||
label = "spi_flash_part2";
|
||||
reg = <0xF00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree For AC5X.
|
||||
*
|
||||
* Copyright (C) 2022 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
#include "ac5-98dx25xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell AC5X SoC";
|
||||
compatible = "marvell,ac5x", "marvell,ac5";
|
||||
};
|
||||
|
||||
&cnm_clock {
|
||||
clock-frequency = <325000000>;
|
||||
};
|
||||
Loading…
Reference in New Issue