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clk: ti: dm814: add clkctrl clock data

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Add data for dm814 clkctrl clocks, and register it within the clkctrl
driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
This commit is contained in:
Tero Kristo 2017-08-24 15:41:37 +03:00
parent fe4ec6513e
commit 26ca2e9738
3 changed files with 42 additions and 0 deletions
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37
drivers/clk/ti/clk-814x.c
View file

@ -9,9 +9,46 @@
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/clk/ti.h> #include <linux/clk/ti.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <dt-bindings/clock/dm814.h>
#include "clock.h" #include "clock.h"
static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
{ DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
{ DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
{ DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
{ DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ 0 },
};
const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
{ 0x48180500, dm814_default_clkctrl_regs },
{ 0x48181400, dm814_alwon_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk dm814_clks[] = { static struct ti_dt_clk dm814_clks[] = {
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
{ .node_name = NULL }, { .node_name = NULL },

4
drivers/clk/ti/clkctrl.c
View file

@ -466,6 +466,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if (of_machine_is_compatible("ti,am438x")) if (of_machine_is_compatible("ti,am438x"))
data = am438x_clkctrl_data; data = am438x_clkctrl_data;
#endif #endif
#ifdef CONFIG_SOC_TI81XX
if (of_machine_is_compatible("ti,dm814"))
data = dm814_clkctrl_data;
#endif
while (data->addr) { while (data->addr) {
if (addr == data->addr) if (addr == data->addr)

1
drivers/clk/ti/clock.h
View file

@ -236,6 +236,7 @@ extern const struct omap_clkctrl_data dra7_clkctrl_data[];
extern const struct omap_clkctrl_data am3_clkctrl_data[]; extern const struct omap_clkctrl_data am3_clkctrl_data[];
extern const struct omap_clkctrl_data am4_clkctrl_data[]; extern const struct omap_clkctrl_data am4_clkctrl_data[];
extern const struct omap_clkctrl_data am438x_clkctrl_data[]; extern const struct omap_clkctrl_data am438x_clkctrl_data[];
extern const struct omap_clkctrl_data dm814_clkctrl_data[];
#define CLKF_SW_SUP BIT(0) #define CLKF_SW_SUP BIT(0)
#define CLKF_HW_SUP BIT(1) #define CLKF_HW_SUP BIT(1)