mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-10-29 23:53:32 +00:00
Code Issues Releases Wiki Activity

imx-drm active plane reconfiguration, cleanup, FSU/IC/IRT/VDIC support

Browse source 
- add active plane reconfiguration support (v4),
   use the atomic_disable callback
 - stop calling disable_plane manually in the plane destroy path
 - let mode cleanup destroy mode objects on driver unbind
 - drop deprecated load/unload drm_driver ops
 - add exclusive fence to plane state, so the atomic helper can
   wait on them, remove the open-coded fence wait from imx-drm
 - add low level deinterlacer (VDIC) support
 - add support for channel linking via the frame synchronisation unit (FSU)
 - add queued image conversion support for memory-to-memory scaling, rotation,
   and color space conversion, using IC and IRT.
 -----BEGIN PGP SIGNATURE-----
 
 iQI0BAABCAAeBQJX3425FxxwLnphYmVsQHBlbmd1dHJvbml4LmRlAAoJEFDCiBxw
 nmDrK1MQAL0KQXTesYqB7ny1r4qQzBhUonk4NpNW6n1TZ8bI3gez+jnsiC6yoPvF
 m2PlcU+yXD4cHAJK9leYpL9zlLujZWn0G1hdyGDwawfB2Gx0hD6v5Ay13As8BJMy
 Z0RsyK87iblP197CD4RTxoKO0NdWZAl8dQSNpKOfhkGaYTR7o+1Tz0iUaoRvw+5s
 r59gVISrl9G/rJzYIMY9RwHNa8s7PMAk2qQo1y9vBH5JUdyprBSJPfN9DfjFaLVc
 SPjwJ3BW6ugEfaGpNmfov5Nmsta/H34Uc1SkyC9F9BLQL0my7tZdT2UiMZRMYAzy
 WIfxQvb0+jMMbRvK/GlhmaMDkaLf2YYpk83a2mHBjj5nHg0oU6oeaKXL2bInLodU
 mLwZFUhUUgf6ALkjq+Tx4wV/D/QAuuQtvQahjs/fQXHgT09kN+PpVUE7Z7l74j0E
 0Hk43ey7juiwrv3DwdZyp26inFaf7vCVspSly1UEukNB3DGthntHt5Q9ySAsCDpv
 fUP4S7QAjvtrzMtvlnCTsPdo2a0e0leCUSVJ/nSf1AkDFJ0S3lOnz6ufxCQwDKly
 99ngGE0O4LLeYd8SbO1rZw0BsuzCQUUvRgVElBlkPjk8UGYPKUgAzH5T6ZBxD8MX
 hkaMfpHJy86EbA7IDUgWszUJjnwyFMX5ZfpA6/FDM2vd3vTVq//C
 =WtaT
 -----END PGP SIGNATURE-----

Merge tag 'imx-drm-next-2016-09-19' of git://git.pengutronix.de/git/pza/linux into drm-next

imx-drm active plane reconfiguration, cleanup, FSU/IC/IRT/VDIC support

- add active plane reconfiguration support (v4),
  use the atomic_disable callback
- stop calling disable_plane manually in the plane destroy path
- let mode cleanup destroy mode objects on driver unbind
- drop deprecated load/unload drm_driver ops
- add exclusive fence to plane state, so the atomic helper can
  wait on them, remove the open-coded fence wait from imx-drm
- add low level deinterlacer (VDIC) support
- add support for channel linking via the frame synchronisation unit (FSU)
- add queued image conversion support for memory-to-memory scaling, rotation,
  and color space conversion, using IC and IRT.

* tag 'imx-drm-next-2016-09-19' of git://git.pengutronix.de/git/pza/linux:
  gpu: ipu-v3: Add queued image conversion support
  gpu: ipu-v3: Add ipu_rot_mode_is_irt()
  gpu: ipu-v3: fix a possible NULL dereference
  drm/imx: parallel-display: detach bridge or panel on unbind
  drm/imx: imx-ldb: detach bridge on unbind
  drm/imx: imx-ldb: detach panel on unbind
  gpu: ipu-v3: Add FSU channel linking support
  gpu: ipu-v3: Add Video Deinterlacer unit
  drm/imx: add exclusive fence to plane state
  drm/imx: fold ipu_plane_disable into ipu_disable_plane
  drm/imx: don't destroy mode objects manually on driver unbind
  drm/imx: drop deprecated load/unload drm_driver ops
  drm/imx: don't call disable_plane in plane destroy path
  drm/imx: Add active plane reconfiguration support
  drm/imx: Use DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET flag
  drm/imx: ipuv3-crtc: Use the callback ->atomic_disable instead of ->disable
  gpu: ipu-v3: Do not wait for DMFC FIFO to clear when disabling DMFC channel
This commit is contained in:
Dave Airlie 2016-09-20 06:24:26 +10:00
commit 26e34d2d8b
16 changed files with 2612 additions and 230 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
drivers/gpu/drm/bridge/dw-hdmi.c
View file

@ -1813,9 +1813,6 @@ void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
/* Disable all interrupts */
hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
hdmi->connector.funcs->destroy(&hdmi->connector);
hdmi->encoder->funcs->destroy(hdmi->encoder);
clk_disable_unprepare(hdmi->iahb_clk);
clk_disable_unprepare(hdmi->isfr_clk);
i2c_put_adapter(hdmi->ddc);

332
drivers/gpu/drm/imx/imx-drm-core.c
View file

@ -64,25 +64,6 @@ static void imx_drm_driver_lastclose(struct drm_device *drm)
drm_fbdev_cma_restore_mode(imxdrm->fbhelper);
}
static int imx_drm_driver_unload(struct drm_device *drm)
{
struct imx_drm_device *imxdrm = drm->dev_private;
drm_kms_helper_poll_fini(drm);
if (imxdrm->fbhelper)
drm_fbdev_cma_fini(imxdrm->fbhelper);
component_unbind_all(drm->dev, drm);
drm_vblank_cleanup(drm);
drm_mode_config_cleanup(drm);
platform_set_drvdata(drm->platformdev, NULL);
return 0;
}
static int imx_drm_enable_vblank(struct drm_device *drm, unsigned int pipe)
{
struct imx_drm_device *imxdrm = drm->dev_private;
@ -146,55 +127,73 @@ static void imx_drm_output_poll_changed(struct drm_device *drm)
drm_fbdev_cma_hotplug_event(imxdrm->fbhelper);
}
static int imx_drm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
{
int ret;
ret = drm_atomic_helper_check_modeset(dev, state);
if (ret)
return ret;
ret = drm_atomic_helper_check_planes(dev, state);
if (ret)
return ret;
/*
* Check modeset again in case crtc_state->mode_changed is
* updated in plane's ->atomic_check callback.
*/
ret = drm_atomic_helper_check_modeset(dev, state);
if (ret)
return ret;
return ret;
}
static int imx_drm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state,
bool nonblock)
{
struct drm_plane_state *plane_state;
struct drm_plane *plane;
struct dma_buf *dma_buf;
int i;
/*
* If the plane fb has an dma-buf attached, fish out the exclusive
* fence for the atomic helper to wait on.
*/
for_each_plane_in_state(state, plane, plane_state, i) {
if ((plane->state->fb != plane_state->fb) && plane_state->fb) {
dma_buf = drm_fb_cma_get_gem_obj(plane_state->fb,
0)->base.dma_buf;
if (!dma_buf)
continue;
plane_state->fence =
reservation_object_get_excl_rcu(dma_buf->resv);
}
}
return drm_atomic_helper_commit(dev, state, nonblock);
}
static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
.fb_create = drm_fb_cma_create,
.output_poll_changed = imx_drm_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
.atomic_check = imx_drm_atomic_check,
.atomic_commit = imx_drm_atomic_commit,
};
static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane_state *plane_state;
struct drm_gem_cma_object *cma_obj;
struct fence *excl;
unsigned shared_count;
struct fence **shared;
unsigned int i, j;
int ret;
/* Wait for fences. */
for_each_crtc_in_state(state, crtc, crtc_state, i) {
plane_state = crtc->primary->state;
if (plane_state->fb) {
cma_obj = drm_fb_cma_get_gem_obj(plane_state->fb, 0);
if (cma_obj->base.dma_buf) {
ret = reservation_object_get_fences_rcu(
cma_obj->base.dma_buf->resv, &excl,
&shared_count, &shared);
if (unlikely(ret))
DRM_ERROR("failed to get fences "
"for buffer\n");
if (excl) {
fence_wait(excl, false);
fence_put(excl);
}
for (j = 0; j < shared_count; i++) {
fence_wait(shared[j], false);
fence_put(shared[j]);
}
}
}
}
drm_atomic_helper_commit_modeset_disables(dev, state);
drm_atomic_helper_commit_planes(dev, state,
DRM_PLANE_COMMIT_ACTIVE_ONLY);
DRM_PLANE_COMMIT_ACTIVE_ONLY |
DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET);
drm_atomic_helper_commit_modeset_enables(dev, state);
@ -209,111 +208,6 @@ static struct drm_mode_config_helper_funcs imx_drm_mode_config_helpers = {
.atomic_commit_tail = imx_drm_atomic_commit_tail,
};
/*
* Main DRM initialisation. This binds, initialises and registers
* with DRM the subcomponents of the driver.
*/
static int imx_drm_driver_load(struct drm_device *drm, unsigned long flags)
{
struct imx_drm_device *imxdrm;
struct drm_connector *connector;
int ret;
imxdrm = devm_kzalloc(drm->dev, sizeof(*imxdrm), GFP_KERNEL);
if (!imxdrm)
return -ENOMEM;
imxdrm->drm = drm;
drm->dev_private = imxdrm;
/*
* enable drm irq mode.
* - with irq_enabled = true, we can use the vblank feature.
*
* P.S. note that we wouldn't use drm irq handler but
* just specific driver own one instead because
* drm framework supports only one irq handler and
* drivers can well take care of their interrupts
*/
drm->irq_enabled = true;
/*
* set max width and height as default value(4096x4096).
* this value would be used to check framebuffer size limitation
* at drm_mode_addfb().
*/
drm->mode_config.min_width = 64;
drm->mode_config.min_height = 64;
drm->mode_config.max_width = 4096;
drm->mode_config.max_height = 4096;
drm->mode_config.funcs = &imx_drm_mode_config_funcs;
drm->mode_config.helper_private = &imx_drm_mode_config_helpers;
drm_mode_config_init(drm);
ret = drm_vblank_init(drm, MAX_CRTC);
if (ret)
goto err_kms;
platform_set_drvdata(drm->platformdev, drm);
/* Now try and bind all our sub-components */
ret = component_bind_all(drm->dev, drm);
if (ret)
goto err_vblank;
/*
* All components are now added, we can publish the connector sysfs
* entries to userspace. This will generate hotplug events and so
* userspace will expect to be able to access DRM at this point.
*/
list_for_each_entry(connector, &drm->mode_config.connector_list, head) {
ret = drm_connector_register(connector);
if (ret) {
dev_err(drm->dev,
"[CONNECTOR:%d:%s] drm_connector_register failed: %d\n",
connector->base.id,
connector->name, ret);
goto err_unbind;
}
}
drm_mode_config_reset(drm);
/*
* All components are now initialised, so setup the fb helper.
* The fb helper takes copies of key hardware information, so the
* crtcs/connectors/encoders must not change after this point.
*/
#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION)
if (legacyfb_depth != 16 && legacyfb_depth != 32) {
dev_warn(drm->dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
legacyfb_depth = 16;
}
imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth,
drm->mode_config.num_crtc, MAX_CRTC);
if (IS_ERR(imxdrm->fbhelper)) {
ret = PTR_ERR(imxdrm->fbhelper);
imxdrm->fbhelper = NULL;
goto err_unbind;
}
#endif
drm_kms_helper_poll_init(drm);
return 0;
err_unbind:
component_unbind_all(drm->dev, drm);
err_vblank:
drm_vblank_cleanup(drm);
err_kms:
drm_mode_config_cleanup(drm);
return ret;
}
/*
* imx_drm_add_crtc - add a new crtc
*/
@ -406,8 +300,6 @@ static const struct drm_ioctl_desc imx_drm_ioctls[] = {
static struct drm_driver imx_drm_driver = {
.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
DRIVER_ATOMIC,
.load = imx_drm_driver_load,
.unload = imx_drm_driver_unload,
.lastclose = imx_drm_driver_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
@ -460,12 +352,122 @@ static int compare_of(struct device *dev, void *data)
static int imx_drm_bind(struct device *dev)
{
return drm_platform_init(&imx_drm_driver, to_platform_device(dev));
struct drm_device *drm;
struct imx_drm_device *imxdrm;
int ret;
drm = drm_dev_alloc(&imx_drm_driver, dev);
if (!drm)
return -ENOMEM;
imxdrm = devm_kzalloc(dev, sizeof(*imxdrm), GFP_KERNEL);
if (!imxdrm) {
ret = -ENOMEM;
goto err_unref;
}
imxdrm->drm = drm;
drm->dev_private = imxdrm;
/*
* enable drm irq mode.
* - with irq_enabled = true, we can use the vblank feature.
*
* P.S. note that we wouldn't use drm irq handler but
* just specific driver own one instead because
* drm framework supports only one irq handler and
* drivers can well take care of their interrupts
*/
drm->irq_enabled = true;
/*
* set max width and height as default value(4096x4096).
* this value would be used to check framebuffer size limitation
* at drm_mode_addfb().
*/
drm->mode_config.min_width = 64;
drm->mode_config.min_height = 64;
drm->mode_config.max_width = 4096;
drm->mode_config.max_height = 4096;
drm->mode_config.funcs = &imx_drm_mode_config_funcs;
drm->mode_config.helper_private = &imx_drm_mode_config_helpers;
drm_mode_config_init(drm);
ret = drm_vblank_init(drm, MAX_CRTC);
if (ret)
goto err_kms;
dev_set_drvdata(dev, drm);
/* Now try and bind all our sub-components */
ret = component_bind_all(dev, drm);
if (ret)
goto err_vblank;
drm_mode_config_reset(drm);
/*
* All components are now initialised, so setup the fb helper.
* The fb helper takes copies of key hardware information, so the
* crtcs/connectors/encoders must not change after this point.
*/
#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION)
if (legacyfb_depth != 16 && legacyfb_depth != 32) {
dev_warn(dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
legacyfb_depth = 16;
}
imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth,
drm->mode_config.num_crtc, MAX_CRTC);
if (IS_ERR(imxdrm->fbhelper)) {
ret = PTR_ERR(imxdrm->fbhelper);
imxdrm->fbhelper = NULL;
goto err_unbind;
}
#endif
drm_kms_helper_poll_init(drm);
ret = drm_dev_register(drm, 0);
if (ret)
goto err_fbhelper;
return 0;
err_fbhelper:
drm_kms_helper_poll_fini(drm);
if (imxdrm->fbhelper)
drm_fbdev_cma_fini(imxdrm->fbhelper);
err_unbind:
component_unbind_all(drm->dev, drm);
err_vblank:
drm_vblank_cleanup(drm);
err_kms:
drm_mode_config_cleanup(drm);
err_unref:
drm_dev_unref(drm);
return ret;
}
static void imx_drm_unbind(struct device *dev)
{
drm_put_dev(dev_get_drvdata(dev));
struct drm_device *drm = dev_get_drvdata(dev);
struct imx_drm_device *imxdrm = drm->dev_private;
drm_dev_unregister(drm);
drm_kms_helper_poll_fini(drm);
if (imxdrm->fbhelper)
drm_fbdev_cma_fini(imxdrm->fbhelper);
drm_mode_config_cleanup(drm);
component_unbind_all(drm->dev, drm);
dev_set_drvdata(dev, NULL);
drm_dev_unref(drm);
}
static const struct component_master_ops imx_drm_ops = {

9
drivers/gpu/drm/imx/imx-ldb.c
View file

@ -757,11 +757,10 @@ static void imx_ldb_unbind(struct device *dev, struct device *master,
for (i = 0; i < 2; i++) {
struct imx_ldb_channel *channel = &imx_ldb->channel[i];
if (!channel->connector.funcs)
continue;
channel->connector.funcs->destroy(&channel->connector);
channel->encoder.funcs->destroy(&channel->encoder);
if (channel->bridge)
drm_bridge_detach(channel->bridge);
if (channel->panel)
drm_panel_detach(channel->panel);
kfree(channel->edid);
i2c_put_adapter(channel->ddc);

3
drivers/gpu/drm/imx/imx-tve.c
View file

@ -685,9 +685,6 @@ static void imx_tve_unbind(struct device *dev, struct device *master,
{
struct imx_tve *tve = dev_get_drvdata(dev);
tve->connector.funcs->destroy(&tve->connector);
tve->encoder.funcs->destroy(&tve->encoder);
if (!IS_ERR(tve->dac_reg))
regulator_disable(tve->dac_reg);
}

17
drivers/gpu/drm/imx/ipuv3-crtc.c
View file

@ -60,7 +60,8 @@ static void ipu_crtc_enable(struct drm_crtc *crtc)
ipu_di_enable(ipu_crtc->di);
}
static void ipu_crtc_disable(struct drm_crtc *crtc)
static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
@ -75,6 +76,9 @@ static void ipu_crtc_disable(struct drm_crtc *crtc)
crtc->state->event = NULL;
}
spin_unlock_irq(&crtc->dev->event_lock);
/* always disable planes on the CRTC */
drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true);
}
static void imx_drm_crtc_reset(struct drm_crtc *crtc)
@ -120,9 +124,14 @@ static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
kfree(to_imx_crtc_state(state));
}
static void imx_drm_crtc_destroy(struct drm_crtc *crtc)
{
imx_drm_remove_crtc(to_ipu_crtc(crtc)->imx_crtc);
}
static const struct drm_crtc_funcs ipu_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.destroy = drm_crtc_cleanup,
.destroy = imx_drm_crtc_destroy,
.page_flip = drm_atomic_helper_page_flip,
.reset = imx_drm_crtc_reset,
.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
@ -241,7 +250,7 @@ static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
.mode_set_nofb = ipu_crtc_mode_set_nofb,
.atomic_check = ipu_crtc_atomic_check,
.atomic_begin = ipu_crtc_atomic_begin,
.disable = ipu_crtc_disable,
.atomic_disable = ipu_crtc_atomic_disable,
.enable = ipu_crtc_enable,
};
@ -409,8 +418,6 @@ static void ipu_drm_unbind(struct device *dev, struct device *master,
{
struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
imx_drm_remove_crtc(ipu_crtc->imx_crtc);
ipu_put_resources(ipu_crtc);
if (ipu_crtc->plane[1])
ipu_plane_put_resources(ipu_crtc->plane[1]);

37
drivers/gpu/drm/imx/ipuv3-plane.c
View file

@ -213,8 +213,12 @@ static void ipu_plane_enable(struct ipu_plane *ipu_plane)
ipu_dp_enable_channel(ipu_plane->dp);
}
static void ipu_plane_disable(struct ipu_plane *ipu_plane)
static int ipu_disable_plane(struct drm_plane *plane)
{
struct ipu_plane *ipu_plane = to_ipu_plane(plane);
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
if (ipu_plane->dp)
@ -223,15 +227,6 @@ static void ipu_plane_disable(struct ipu_plane *ipu_plane)
ipu_dmfc_disable_channel(ipu_plane->dmfc);
if (ipu_plane->dp)
ipu_dp_disable(ipu_plane->ipu);
}
static int ipu_disable_plane(struct drm_plane *plane)
{
struct ipu_plane *ipu_plane = to_ipu_plane(plane);
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
ipu_plane_disable(ipu_plane);
return 0;
}
@ -242,7 +237,6 @@ static void ipu_plane_destroy(struct drm_plane *plane)
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
ipu_disable_plane(plane);
drm_plane_cleanup(plane);
kfree(ipu_plane);
}
@ -319,13 +313,16 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/*
* since we cannot touch active IDMAC channels, we do not support
* resizing the enabled plane or changing its format
* We support resizing active plane or changing its format by
* forcing CRTC mode change in plane's ->atomic_check callback
* and disabling all affected active planes in CRTC's ->atomic_disable
* callback. The planes will be reenabled in plane's ->atomic_update
* callback.
*/
if (old_fb && (state->src_w != old_state->src_w ||
state->src_h != old_state->src_h ||
fb->pixel_format != old_fb->pixel_format))
return -EINVAL;
crtc_state->mode_changed = true;
eba = drm_plane_state_to_eba(state);
@ -336,7 +333,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
if (old_fb && fb->pitches[0] != old_fb->pitches[0])
return -EINVAL;
crtc_state->mode_changed = true;
switch (fb->pixel_format) {
case DRM_FORMAT_YUV420:
@ -372,7 +369,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
if (old_fb && old_fb->pitches[1] != fb->pitches[1])
return -EINVAL;
crtc_state->mode_changed = true;
}
return 0;
@ -392,8 +389,12 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
enum ipu_color_space ics;
if (old_state->fb) {
ipu_plane_atomic_set_base(ipu_plane, old_state);
return;
struct drm_crtc_state *crtc_state = state->crtc->state;
if (!drm_atomic_crtc_needs_modeset(crtc_state)) {
ipu_plane_atomic_set_base(ipu_plane, old_state);
return;
}
}
switch (ipu_plane->dp_flow) {

6
drivers/gpu/drm/imx/parallel-display.c
View file

@ -293,8 +293,10 @@ static void imx_pd_unbind(struct device *dev, struct device *master,
{
struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
imxpd->encoder.funcs->destroy(&imxpd->encoder);
imxpd->connector.funcs->destroy(&imxpd->connector);
if (imxpd->bridge)
drm_bridge_detach(imxpd->bridge);
if (imxpd->panel)
drm_panel_detach(imxpd->panel);
kfree(imxpd->edid);
}

3
drivers/gpu/ipu-v3/Makefile
View file

@ -1,4 +1,5 @@
obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o
imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-csi.o ipu-dc.o ipu-di.o \
ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-smfc.o
ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-image-convert.o \
ipu-smfc.o ipu-vdi.o

157
drivers/gpu/ipu-v3/ipu-common.c
View file

@ -730,6 +730,137 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
}
EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
/* Frame Synchronization Unit Channel Linking */
struct fsu_link_reg_info {
int chno;
u32 reg;
u32 mask;
u32 val;
};
struct fsu_link_info {
struct fsu_link_reg_info src;
struct fsu_link_reg_info sink;
};
static const struct fsu_link_info fsu_link_info[] = {
{
.src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
.sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
}, {
.src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
.sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
}, {
.src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
.sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
}, {
.src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
.sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
},
};
static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
{
int i;
for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
if (src == fsu_link_info[i].src.chno &&
sink == fsu_link_info[i].sink.chno)
return &fsu_link_info[i];
}
return NULL;
}
/*
* Links a source channel to a sink channel in the FSU.
*/
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
{
const struct fsu_link_info *link;
u32 src_reg, sink_reg;
unsigned long flags;
link = find_fsu_link_info(src_ch, sink_ch);
if (!link)
return -EINVAL;
spin_lock_irqsave(&ipu->lock, flags);
if (link->src.mask) {
src_reg = ipu_cm_read(ipu, link->src.reg);
src_reg &= ~link->src.mask;
src_reg |= link->src.val;
ipu_cm_write(ipu, src_reg, link->src.reg);
}
if (link->sink.mask) {
sink_reg = ipu_cm_read(ipu, link->sink.reg);
sink_reg &= ~link->sink.mask;
sink_reg |= link->sink.val;
ipu_cm_write(ipu, sink_reg, link->sink.reg);
}
spin_unlock_irqrestore(&ipu->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_fsu_link);
/*
* Unlinks source and sink channels in the FSU.
*/
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
{
const struct fsu_link_info *link;
u32 src_reg, sink_reg;
unsigned long flags;
link = find_fsu_link_info(src_ch, sink_ch);
if (!link)
return -EINVAL;
spin_lock_irqsave(&ipu->lock, flags);
if (link->src.mask) {
src_reg = ipu_cm_read(ipu, link->src.reg);
src_reg &= ~link->src.mask;
ipu_cm_write(ipu, src_reg, link->src.reg);
}
if (link->sink.mask) {
sink_reg = ipu_cm_read(ipu, link->sink.reg);
sink_reg &= ~link->sink.mask;
ipu_cm_write(ipu, sink_reg, link->sink.reg);
}
spin_unlock_irqrestore(&ipu->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
/* Link IDMAC channels in the FSU */
int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
{
return ipu_fsu_link(src->ipu, src->num, sink->num);
}
EXPORT_SYMBOL_GPL(ipu_idmac_link);
/* Unlink IDMAC channels in the FSU */
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
{
return ipu_fsu_unlink(src->ipu, src->num, sink->num);
}
EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
struct ipu_devtype {
const char *name;
unsigned long cm_ofs;
@ -839,6 +970,20 @@ static int ipu_submodules_init(struct ipu_soc *ipu,
goto err_ic;
}
ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
IPU_CONF_IC_INPUT);
if (ret) {
unit = "vdi";
goto err_vdi;
}
ret = ipu_image_convert_init(ipu, dev);
if (ret) {
unit = "image_convert";
goto err_image_convert;
}
ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
IPU_CONF_DI0_EN, ipu_clk);
if (ret) {
@ -893,6 +1038,10 @@ static int ipu_submodules_init(struct ipu_soc *ipu,
err_di_1:
ipu_di_exit(ipu, 0);
err_di_0:
ipu_image_convert_exit(ipu);
err_image_convert:
ipu_vdi_exit(ipu);
err_vdi:
ipu_ic_exit(ipu);
err_ic:
ipu_csi_exit(ipu, 1);
@ -977,6 +1126,8 @@ static void ipu_submodules_exit(struct ipu_soc *ipu)
ipu_dc_exit(ipu);
ipu_di_exit(ipu, 1);
ipu_di_exit(ipu, 0);
ipu_image_convert_exit(ipu);
ipu_vdi_exit(ipu);
ipu_ic_exit(ipu);
ipu_csi_exit(ipu, 1);
ipu_csi_exit(ipu, 0);
@ -1213,8 +1364,6 @@ EXPORT_SYMBOL_GPL(ipu_dump);
static int ipu_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(imx_ipu_dt_ids, &pdev->dev);
struct device_node *np = pdev->dev.of_node;
struct ipu_soc *ipu;
struct resource *res;
@ -1222,7 +1371,9 @@ static int ipu_probe(struct platform_device *pdev)
int i, ret, irq_sync, irq_err;
const struct ipu_devtype *devtype;
devtype = of_id->data;
devtype = of_device_get_match_data(&pdev->dev);
if (!devtype)
return -EINVAL;
irq_sync = platform_get_irq(pdev, 0);
irq_err = platform_get_irq(pdev, 1);

18
drivers/gpu/ipu-v3/ipu-dmfc.c
View file

@ -123,20 +123,6 @@ int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
}
EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
static void ipu_dmfc_wait_fifos(struct ipu_dmfc_priv *priv)
{
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
while ((readl(priv->base + DMFC_STAT) & 0x02fff000) != 0x02fff000) {
if (time_after(jiffies, timeout)) {
dev_warn(priv->dev,
"Timeout waiting for DMFC FIFOs to clear\n");
break;
}
cpu_relax();
}
}
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
{
struct ipu_dmfc_priv *priv = dmfc->priv;
@ -145,10 +131,8 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
priv->use_count--;
if (!priv->use_count) {
ipu_dmfc_wait_fifos(priv);
if (!priv->use_count)
ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
}
if (priv->use_count < 0)
priv->use_count = 0;

2
drivers/gpu/ipu-v3/ipu-ic.c
View file

@ -619,7 +619,7 @@ int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2);
ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3);
if (rot >= IPU_ROTATE_90_RIGHT)
if (ipu_rot_mode_is_irt(rot))
ic->rotation = true;
unlock:

1709
drivers/gpu/ipu-v3/ipu-image-convert.c Normal file
View file

File diff suppressed because it is too large Load diff

38
drivers/gpu/ipu-v3/ipu-prv.h
View file

@ -75,6 +75,33 @@ struct ipu_soc;
#define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n))
#define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n))
/* FS_PROC_FLOW1 */
#define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0)
#define FS_PRPENC_ROT_SRC_SEL_ENC (0x7 << 0)
#define FS_PRPVF_ROT_SRC_SEL_MASK (0xf << 8)
#define FS_PRPVF_ROT_SRC_SEL_VF (0x8 << 8)
#define FS_PP_SRC_SEL_MASK (0xf << 12)
#define FS_PP_ROT_SRC_SEL_MASK (0xf << 16)
#define FS_PP_ROT_SRC_SEL_PP (0x5 << 16)
#define FS_VDI1_SRC_SEL_MASK (0x3 << 20)
#define FS_VDI3_SRC_SEL_MASK (0x3 << 20)
#define FS_PRP_SRC_SEL_MASK (0xf << 24)
#define FS_VDI_SRC_SEL_MASK (0x3 << 28)
#define FS_VDI_SRC_SEL_CSI_DIRECT (0x1 << 28)
#define FS_VDI_SRC_SEL_VDOA (0x2 << 28)
/* FS_PROC_FLOW2 */
#define FS_PRP_ENC_DEST_SEL_MASK (0xf << 0)
#define FS_PRP_ENC_DEST_SEL_IRT_ENC (0x1 << 0)
#define FS_PRPVF_DEST_SEL_MASK (0xf << 4)
#define FS_PRPVF_DEST_SEL_IRT_VF (0x1 << 4)
#define FS_PRPVF_ROT_DEST_SEL_MASK (0xf << 8)
#define FS_PP_DEST_SEL_MASK (0xf << 12)
#define FS_PP_DEST_SEL_IRT_PP (0x3 << 12)
#define FS_PP_ROT_DEST_SEL_MASK (0xf << 16)
#define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20)
#define FS_PRP_DEST_SEL_MASK (0xf << 24)
#define IPU_DI0_COUNTER_RELEASE (1 << 24)
#define IPU_DI1_COUNTER_RELEASE (1 << 25)
@ -138,6 +165,8 @@ struct ipu_dc_priv;
struct ipu_dmfc_priv;
struct ipu_di;
struct ipu_ic_priv;
struct ipu_vdi;
struct ipu_image_convert_priv;
struct ipu_smfc_priv;
struct ipu_devtype;
@ -170,6 +199,8 @@ struct ipu_soc {
struct ipu_di *di_priv[2];
struct ipu_csi *csi_priv[2];
struct ipu_ic_priv *ic_priv;
struct ipu_vdi *vdi_priv;
struct ipu_image_convert_priv *image_convert_priv;
struct ipu_smfc_priv *smfc_priv;
};
@ -200,6 +231,13 @@ int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
unsigned long base, unsigned long tpmem_base);
void ipu_ic_exit(struct ipu_soc *ipu);
int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
unsigned long base, u32 module);
void ipu_vdi_exit(struct ipu_soc *ipu);
int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
void ipu_image_convert_exit(struct ipu_soc *ipu);
int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
unsigned long base, u32 module, struct clk *ipu_clk);
void ipu_di_exit(struct ipu_soc *ipu, int id);

243
drivers/gpu/ipu-v3/ipu-vdi.c Normal file
View file

@ -0,0 +1,243 @@
/*
* Copyright (C) 2012-2016 Mentor Graphics Inc.
* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/io.h>
#include "ipu-prv.h"
struct ipu_vdi {
void __iomem *base;
u32 module;
spinlock_t lock;
int use_count;
struct ipu_soc *ipu;
};
/* VDI Register Offsets */
#define VDI_FSIZE 0x0000
#define VDI_C 0x0004
/* VDI Register Fields */
#define VDI_C_CH_420 (0 << 1)
#define VDI_C_CH_422 (1 << 1)
#define VDI_C_MOT_SEL_MASK (0x3 << 2)
#define VDI_C_MOT_SEL_FULL (2 << 2)
#define VDI_C_MOT_SEL_LOW (1 << 2)
#define VDI_C_MOT_SEL_MED (0 << 2)
#define VDI_C_BURST_SIZE1_4 (3 << 4)
#define VDI_C_BURST_SIZE2_4 (3 << 8)
#define VDI_C_BURST_SIZE3_4 (3 << 12)
#define VDI_C_BURST_SIZE_MASK 0xF
#define VDI_C_BURST_SIZE1_OFFSET 4
#define VDI_C_BURST_SIZE2_OFFSET 8
#define VDI_C_BURST_SIZE3_OFFSET 12
#define VDI_C_VWM1_SET_1 (0 << 16)
#define VDI_C_VWM1_SET_2 (1 << 16)
#define VDI_C_VWM1_CLR_2 (1 << 19)
#define VDI_C_VWM3_SET_1 (0 << 22)
#define VDI_C_VWM3_SET_2 (1 << 22)
#define VDI_C_VWM3_CLR_2 (1 << 25)
#define VDI_C_TOP_FIELD_MAN_1 (1 << 30)
#define VDI_C_TOP_FIELD_AUTO_1 (1 << 31)
static inline u32 ipu_vdi_read(struct ipu_vdi *vdi, unsigned int offset)
{
return readl(vdi->base + offset);
}
static inline void ipu_vdi_write(struct ipu_vdi *vdi, u32 value,
unsigned int offset)
{
writel(value, vdi->base + offset);
}
void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field)
{
bool top_field_0 = false;
unsigned long flags;
u32 reg;
switch (field) {
case V4L2_FIELD_INTERLACED_TB:
case V4L2_FIELD_SEQ_TB:
case V4L2_FIELD_TOP:
top_field_0 = true;
break;
case V4L2_FIELD_INTERLACED_BT:
case V4L2_FIELD_SEQ_BT:
case V4L2_FIELD_BOTTOM:
top_field_0 = false;
break;
default:
top_field_0 = (std & V4L2_STD_525_60) ? true : false;
break;
}
spin_lock_irqsave(&vdi->lock, flags);
reg = ipu_vdi_read(vdi, VDI_C);
if (top_field_0)
reg &= ~VDI_C_TOP_FIELD_MAN_1;
else
reg |= VDI_C_TOP_FIELD_MAN_1;
ipu_vdi_write(vdi, reg, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_set_field_order);
void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel)
{
unsigned long flags;
u32 reg;
spin_lock_irqsave(&vdi->lock, flags);
reg = ipu_vdi_read(vdi, VDI_C);
reg &= ~VDI_C_MOT_SEL_MASK;
switch (motion_sel) {
case MED_MOTION:
reg |= VDI_C_MOT_SEL_MED;
break;
case HIGH_MOTION:
reg |= VDI_C_MOT_SEL_FULL;
break;
default:
reg |= VDI_C_MOT_SEL_LOW;
break;
}
ipu_vdi_write(vdi, reg, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_set_motion);
void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres)
{
unsigned long flags;
u32 pixel_fmt, reg;
spin_lock_irqsave(&vdi->lock, flags);
reg = ((yres - 1) << 16) | (xres - 1);
ipu_vdi_write(vdi, reg, VDI_FSIZE);
/*
* Full motion, only vertical filter is used.
* Burst size is 4 accesses
*/
if (code == MEDIA_BUS_FMT_UYVY8_2X8 ||
code == MEDIA_BUS_FMT_UYVY8_1X16 ||
code == MEDIA_BUS_FMT_YUYV8_2X8 ||
code == MEDIA_BUS_FMT_YUYV8_1X16)
pixel_fmt = VDI_C_CH_422;
else
pixel_fmt = VDI_C_CH_420;
reg = ipu_vdi_read(vdi, VDI_C);
reg |= pixel_fmt;
reg |= VDI_C_BURST_SIZE2_4;
reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_CLR_2;
reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_CLR_2;
ipu_vdi_write(vdi, reg, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_setup);
void ipu_vdi_unsetup(struct ipu_vdi *vdi)
{
unsigned long flags;
spin_lock_irqsave(&vdi->lock, flags);
ipu_vdi_write(vdi, 0, VDI_FSIZE);
ipu_vdi_write(vdi, 0, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_unsetup);
int ipu_vdi_enable(struct ipu_vdi *vdi)
{
unsigned long flags;
spin_lock_irqsave(&vdi->lock, flags);
if (!vdi->use_count)
ipu_module_enable(vdi->ipu, vdi->module);
vdi->use_count++;
spin_unlock_irqrestore(&vdi->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_vdi_enable);
int ipu_vdi_disable(struct ipu_vdi *vdi)
{
unsigned long flags;
spin_lock_irqsave(&vdi->lock, flags);
if (vdi->use_count) {
if (!--vdi->use_count)
ipu_module_disable(vdi->ipu, vdi->module);
}
spin_unlock_irqrestore(&vdi->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_vdi_disable);
struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu)
{
return ipu->vdi_priv;
}
EXPORT_SYMBOL_GPL(ipu_vdi_get);
void ipu_vdi_put(struct ipu_vdi *vdi)
{
}
EXPORT_SYMBOL_GPL(ipu_vdi_put);
int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
unsigned long base, u32 module)
{
struct ipu_vdi *vdi;
vdi = devm_kzalloc(dev, sizeof(*vdi), GFP_KERNEL);
if (!vdi)
return -ENOMEM;
ipu->vdi_priv = vdi;
spin_lock_init(&vdi->lock);
vdi->module = module;
vdi->base = devm_ioremap(dev, base, PAGE_SIZE);
if (!vdi->base)
return -ENOMEM;
dev_dbg(dev, "VDI base: 0x%08lx remapped to %p\n", base, vdi->base);
vdi->ipu = ipu;
return 0;
}
void ipu_vdi_exit(struct ipu_soc *ipu)
{
}

207
include/video/imx-ipu-image-convert.h Normal file
View file

@ -0,0 +1,207 @@
/*
* Copyright (C) 2012-2016 Mentor Graphics Inc.
*
* i.MX Queued image conversion support, with tiling and rotation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef __IMX_IPU_IMAGE_CONVERT_H__
#define __IMX_IPU_IMAGE_CONVERT_H__
#include <video/imx-ipu-v3.h>
struct ipu_image_convert_ctx;
/**
* struct ipu_image_convert_run - image conversion run request struct
*
* @ctx: the conversion context
* @in_phys: dma addr of input image buffer for this run
* @out_phys: dma addr of output image buffer for this run
* @status: completion status of this run
*/
struct ipu_image_convert_run {
struct ipu_image_convert_ctx *ctx;
dma_addr_t in_phys;
dma_addr_t out_phys;
int status;
/* internal to image converter, callers don't touch */
struct list_head list;
};
/**
* ipu_image_convert_cb_t - conversion callback function prototype
*
* @run: the completed conversion run pointer
* @ctx: a private context pointer for the callback
*/
typedef void (*ipu_image_convert_cb_t)(struct ipu_image_convert_run *run,
void *ctx);
/**
* ipu_image_convert_enum_format() - enumerate the image converter's
* supported input and output pixel formats.
*
* @index: pixel format index
* @fourcc: v4l2 fourcc for this index
*
* Returns 0 with a valid index and fills in v4l2 fourcc, -EINVAL otherwise.
*
* In V4L2, drivers can call ipu_image_enum_format() in .enum_fmt.
*/
int ipu_image_convert_enum_format(int index, u32 *fourcc);
/**
* ipu_image_convert_adjust() - adjust input/output images to IPU restrictions.
*
* @in: input image format, adjusted on return
* @out: output image format, adjusted on return
* @rot_mode: rotation mode
*
* In V4L2, drivers can call ipu_image_convert_adjust() in .try_fmt.
*/
void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode);
/**
* ipu_image_convert_verify() - verify that input/output image formats
* and rotation mode meet IPU restrictions.
*
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
*
* Returns 0 if the formats and rotation mode meet IPU restrictions,
* -EINVAL otherwise.
*/
int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode);
/**
* ipu_image_convert_prepare() - prepare a conversion context.
*
* @ipu: the IPU handle to use for the conversions
* @ic_task: the IC task to use for the conversions
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
* @complete: run completion callback
* @complete_context: a context pointer for the completion callback
*
* Returns an opaque conversion context pointer on success, error pointer
* on failure. The input/output formats and rotation mode must already meet
* IPU retrictions.
*
* In V4L2, drivers should call ipu_image_convert_prepare() at streamon.
*/
struct ipu_image_convert_ctx *
ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode,
ipu_image_convert_cb_t complete,
void *complete_context);
/**
* ipu_image_convert_unprepare() - unprepare a conversion context.
*
* @ctx: the conversion context pointer to unprepare
*
* Aborts any active or pending conversions for this context and
* frees the context. Any currently active or pending runs belonging
* to this context are returned via the completion callback with an
* error run status.
*
* In V4L2, drivers should call ipu_image_convert_unprepare() at
* streamoff.
*/
void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx);
/**
* ipu_image_convert_queue() - queue a conversion run
*
* @run: the run request pointer
*
* ipu_image_convert_run must be dynamically allocated (_not_ as a local
* var) by callers and filled in with a previously prepared conversion
* context handle and the dma addr's of the input and output image buffers
* for this conversion run.
*
* When this conversion completes, the run pointer is returned via the
* completion callback. The caller is responsible for freeing the run
* object after it completes.
*
* In V4L2, drivers should call ipu_image_convert_queue() while
* streaming to queue the conversion of a received input buffer.
* For example mem2mem devices this would be called in .device_run.
*/
int ipu_image_convert_queue(struct ipu_image_convert_run *run);
/**
* ipu_image_convert_abort() - abort conversions
*
* @ctx: the conversion context pointer
*
* This will abort any active or pending conversions for this context.
* Any currently active or pending runs belonging to this context are
* returned via the completion callback with an error run status.
*/
void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx);
/**
* ipu_image_convert() - asynchronous image conversion request
*
* @ipu: the IPU handle to use for the conversion
* @ic_task: the IC task to use for the conversion
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
* @complete: run completion callback
* @complete_context: a context pointer for the completion callback
*
* Request a single image conversion. Returns the run that has been queued.
* A conversion context is automatically created and is available in run->ctx.
* As with ipu_image_convert_prepare(), the input/output formats and rotation
* mode must already meet IPU retrictions.
*
* On successful return the caller can queue more run requests if needed, using
* the prepared context in run->ctx. The caller is responsible for unpreparing
* the context when no more conversion requests are needed.
*/
struct ipu_image_convert_run *
ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode,
ipu_image_convert_cb_t complete,
void *complete_context);
/**
* ipu_image_convert_sync() - synchronous single image conversion request
*
* @ipu: the IPU handle to use for the conversion
* @ic_task: the IC task to use for the conversion
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
*
* Carry out a single image conversion. Returns when the conversion
* completes. The input/output formats and rotation mode must already
* meet IPU retrictions. The created context is automatically unprepared
* and the run freed on return.
*/
int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode);
#endif /* __IMX_IPU_IMAGE_CONVERT_H__ */

58
include/video/imx-ipu-v3.h
View file

@ -63,23 +63,41 @@ enum ipu_csi_dest {
/*
* Enumeration of IPU rotation modes
*/
#define IPU_ROT_BIT_VFLIP (1 << 0)
#define IPU_ROT_BIT_HFLIP (1 << 1)
#define IPU_ROT_BIT_90 (1 << 2)
enum ipu_rotate_mode {
IPU_ROTATE_NONE = 0,
IPU_ROTATE_VERT_FLIP,
IPU_ROTATE_HORIZ_FLIP,
IPU_ROTATE_180,
IPU_ROTATE_90_RIGHT,
IPU_ROTATE_90_RIGHT_VFLIP,
IPU_ROTATE_90_RIGHT_HFLIP,
IPU_ROTATE_90_LEFT,
IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
};
/* 90-degree rotations require the IRT unit */
#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
enum ipu_color_space {
IPUV3_COLORSPACE_RGB,
IPUV3_COLORSPACE_YUV,
IPUV3_COLORSPACE_UNKNOWN,
};
/*
* Enumeration of VDI MOTION select
*/
enum ipu_motion_sel {
MOTION_NONE = 0,
LOW_MOTION,
MED_MOTION,
HIGH_MOTION,
};
struct ipuv3_channel;
enum ipu_channel_irq {
@ -97,6 +115,14 @@ enum ipu_channel_irq {
#define IPUV3_CHANNEL_CSI2 2
#define IPUV3_CHANNEL_CSI3 3
#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
/*
* NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
* but the direct CSI->VDI linking is handled the same way as IDMAC
* channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
* these channel names are used to support the direct CSI->VDI link.
*/
#define IPUV3_CHANNEL_CSI_DIRECT 6
#define IPUV3_CHANNEL_CSI_VDI_PREV 7
#define IPUV3_CHANNEL_MEM_VDI_PREV 8
#define IPUV3_CHANNEL_MEM_VDI_CUR 9
#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
@ -133,6 +159,7 @@ enum ipu_channel_irq {
#define IPUV3_CHANNEL_ROT_PP_MEM 50
#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
#define IPUV3_NUM_CHANNELS 64
int ipu_map_irq(struct ipu_soc *ipu, int irq);
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
@ -176,6 +203,10 @@ int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
/*
* IPU Channel Parameter Memory (cpmem) functions
@ -334,6 +365,19 @@ struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
void ipu_ic_put(struct ipu_ic *ic);
void ipu_ic_dump(struct ipu_ic *ic);
/*
* IPU Video De-Interlacer (vdi) functions
*/
struct ipu_vdi;
void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
void ipu_vdi_unsetup(struct ipu_vdi *vdi);
int ipu_vdi_enable(struct ipu_vdi *vdi);
int ipu_vdi_disable(struct ipu_vdi *vdi);
struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
void ipu_vdi_put(struct ipu_vdi *vdi);
/*
* IPU Sensor Multiple FIFO Controller (SMFC) functions
*/