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perf vendor events: Update metrics for Jaketown

Browse source 
Based on TMA_metrics-full.csv version 4.3 at 01.org:
    https://download.01.org/perfmon/
Events are still at version 20:
    https://download.01.org/perfmon/JKT
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf

Tested:

Not tested on a Jaketown, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-18-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2022-01-31 17:58:49 -08:00 committed by Arnaldo Carvalho de Melo
parent 70d90a6a57
commit 2782403c08
8 changed files with 3251 additions and 3260 deletions
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2230
tools/perf/pmu-events/arch/x86/jaketown/cache.json
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tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
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@ -1,138 +1,138 @@
[
{
"EventCode": "0xC1",
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xC1",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xC1",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of X87 assists due to output value.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of X87 assists due to input value.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of SIMD FP assists due to Output values.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of SIMD FP assists due to input values.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x11",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x11",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x1e",
"EventName": "FP_ASSIST.ANY",
"SampleAfterValue": "100003",
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1e"
},
{
"BriefDescription": "Number of SIMD FP assists due to input values.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x11",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]

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tools/perf/pmu-events/arch/x86/jaketown/frontend.json
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@ -1,305 +1,314 @@
[
{
"EventCode": "0x80",
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
"UMask": "0x1f"
},
{
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
"EventCode": "0x80",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "IDQ.MITE_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.",
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "IDQ.MS_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"CounterMask": "3",
"CounterHTOff": "0,1,2,3"
},
{
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"SampleAfterValue": "2000003",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
"EventCode": "0xAB",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DSB_FILL.OTHER_CANCEL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xAC",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "IDQ.MITE_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "IDQ.DSB_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "IDQ.MS_DSB_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EdgeDetect": "1",
"EventName": "IDQ.MS_DSB_OCCUR",
"SampleAfterValue": "2000003",
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"CounterMask": "2",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x9C",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x18",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x18",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x24",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
"CounterMask": "4",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"Counter": "0,1,2,3",
"UMask": "0x24",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles MITE is delivering any Uop.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xAC",
"Counter": "0,1,2,3",
"UMask": "0xa",
"EventName": "DSB_FILL.ALL_CANCEL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0xa"
},
{
"EventCode": "0x9C",
"Invert": "1",
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
"UMask": "0x8"
},
{
"EventCode": "0x79",
"BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
"Counter": "0,1,2,3",
"UMask": "0x3c",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAC",
"EventName": "DSB_FILL.OTHER_CANCEL",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x24"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x24"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x3c"
},
{
"EventCode": "0x79",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
"Counter": "0,1,2,3",
"UMask": "0x30",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_OCCUR",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]

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tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
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@ -1,142 +1,132 @@
[
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Frontend_Bound",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
},
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Frontend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Bad_Speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Bad_Speculation_SMT",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )",
"MetricConstraint": "NO_NMI_WATCHDOG",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )",
"MetricGroup": "TopdownL1",
"MetricName": "Backend_Bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Backend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Retiring",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. "
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. "
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Retiring_SMT",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TopDownL1",
"MetricGroup": "Ret;Summary",
"MetricName": "IPC"
},
{
"BriefDescription": "Uops Per Instruction",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Retire",
"MetricGroup": "Pipeline;Ret;Retire",
"MetricName": "UPI"
},
{
"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions",
"MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )",
"MetricGroup": "PGO;IcMiss",
"MetricName": "IFetch_Line_Utilization"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fetch_BW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
"MetricGroup": "Pipeline;Summary",
"MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "Pipeline;Mem",
"MetricName": "CPI"
},
{
"BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary",
"MetricGroup": "Pipeline",
"MetricName": "CLKS"
},
{
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
"MetricExpr": "4 * cycles",
"MetricGroup": "TopDownL1",
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TmaL1",
"MetricName": "SLOTS"
},
{
"BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
"MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopDownL1_SMT",
"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "TmaL1_SMT",
"MetricName": "SLOTS_SMT"
},
{
"BriefDescription": "Total number of retired Instructions",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary",
"MetricName": "Instructions"
"BriefDescription": "The ratio of Executed- by Issued-Uops",
"MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY",
"MetricGroup": "Cor;Pipeline",
"MetricName": "Execute_per_Issue",
"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
"BriefDescription": "Instructions Per Cycle (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / cycles",
"MetricGroup": "SMT",
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Ret;SMT;TmaL1",
"MetricName": "CoreIPC"
},
{
"BriefDescription": "Instructions Per Cycle (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "SMT",
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Ret;SMT;TmaL1_SMT",
"MetricName": "CoreIPC_SMT"
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles",
"MetricGroup": "FLOPS",
"MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Ret;Flops",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "FLOPS_SMT",
"MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Ret;Flops_SMT",
"MetricName": "FLOPc_SMT"
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
"MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
"MetricGroup": "Pipeline",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
@ -145,16 +135,34 @@
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
{
"BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary;TmaL1",
"MetricName": "Instructions"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"MetricGroup": "Summary",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
"MetricGroup": "Summary;Power",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
"MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time",
"MetricGroup": "FLOPS;Summary",
"MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs"
},
{
@ -165,28 +173,40 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT;Summary",
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
{
"BriefDescription": "Fraction of cycles spent in Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary",
"BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "OS",
"MetricName": "Kernel_Utilization"
},
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
"MetricGroup": "OS",
"MetricName": "Kernel_CPI"
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time",
"MetricGroup": "Memory_BW",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
"MetricExpr": "cbox_0@event\\=0x0@",
"MetricGroup": "",
"MetricGroup": "SoC",
"MetricName": "Socket_CLKS"
},
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
{
"BriefDescription": "C3 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",

740
tools/perf/pmu-events/arch/x86/jaketown/memory.json
View file

@ -1,422 +1,422 @@
[
{
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x4",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
"SampleAfterValue": "100003",
"BriefDescription": "Loads with latency value being above 4 .",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x2"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x8",
"BriefDescription": "Loads with latency value being above 128.",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"SampleAfterValue": "50021",
"BriefDescription": "Loads with latency value being above 8.",
"TakenAlone": "1",
"CounterHTOff": "3"
},
{
"PEBS": "2",
"CounterHTOff": "3",
"EventCode": "0xCD",
"MSRValue": "0x10",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"SampleAfterValue": "20011",
"BriefDescription": "Loads with latency value being above 16.",
"TakenAlone": "1",
"CounterHTOff": "3"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x20",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"SampleAfterValue": "100007",
"BriefDescription": "Loads with latency value being above 32.",
"TakenAlone": "1",
"CounterHTOff": "3"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x40",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"SampleAfterValue": "2003",
"BriefDescription": "Loads with latency value being above 64.",
"TakenAlone": "1",
"CounterHTOff": "3"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x80",
"Counter": "3",
"UMask": "0x1",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1009",
"BriefDescription": "Loads with latency value being above 128.",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x100",
"BriefDescription": "Loads with latency value being above 16.",
"Counter": "3",
"UMask": "0x1",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "20011",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256.",
"Counter": "3",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "503",
"BriefDescription": "Loads with latency value being above 256.",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"PEBS": "2",
"EventCode": "0xCD",
"MSRValue": "0x200",
"BriefDescription": "Loads with latency value being above 32.",
"Counter": "3",
"UMask": "0x1",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4 .",
"Counter": "3",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "100003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512.",
"Counter": "3",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"SampleAfterValue": "101",
"BriefDescription": "Loads with latency value being above 512.",
"TakenAlone": "1",
"CounterHTOff": "3"
},
{
"MSRValue": "0x200",
"PEBS": "2",
"EventCode": "0xCD",
"Counter": "3",
"UMask": "0x2",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
"PRECISE_STORE": "1",
"SampleAfterValue": "101",
"TakenAlone": "1",
"CounterHTOff": "3"
"UMask": "0x1"
},
{
"EventCode": "0x05",
"BriefDescription": "Loads with latency value being above 64.",
"Counter": "3",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8.",
"Counter": "3",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "50021",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
"Counter": "3",
"CounterHTOff": "3",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
"PEBS": "2",
"PRECISE_STORE": "1",
"SampleAfterValue": "2000003",
"TakenAlone": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"SampleAfterValue": "2000003",
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x05",
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"SampleAfterValue": "2000003",
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3fffc20004",
"BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand code reads that miss the LLC",
"CounterHTOff": "0,1,2,3"
},
{
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x600400004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x67f800004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x87f820004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x107fc00004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x67fc00001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3fffc20001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that miss in the LLC",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x600400001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x67f800001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x87f820001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x107fc00001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3fffc20040",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x67fc00010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3fffc20010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x600400010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x67f800010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x87f820010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x107fc00010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3fffc20200",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3fffc20080",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x600400077",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100003",
"BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x3FFFC20077",
"Counter": "0,1,2,3",
"UMask": "0x1",
"Offcore": "1",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC20077",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x187FC20077",
"BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400077",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x187FC20077",
"Offcore": "1",
"SampleAfterValue": "100003",
"BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
"CounterHTOff": "0,1,2,3"
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67fc00001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss in the LLC",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20040",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67fc00010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x67f800010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107fc00010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87f820010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20200",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3fffc20080",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
]

58
tools/perf/pmu-events/arch/x86/jaketown/other.json
View file

@ -1,58 +1,58 @@
[
{
"EventCode": "0x17",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
"BriefDescription": "Valid instructions written to IQ per cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x5C",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0_TRANS",
"SampleAfterValue": "100007",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x5C",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0x4E",
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
"Counter": "0,1,2,3",
"UMask": "0x2",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4E",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"EventCode": "0x63",
"BriefDescription": "Valid instructions written to IQ per cycle.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x17",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
}
]

2312
tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
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222
tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
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@ -1,149 +1,149 @@
[
{
"EventCode": "0xAE",
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x4F",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ITLB_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x08",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x2"
},
{
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"EventCode": "0x49",
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0x49",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x10"
},
{
"EventCode": "0xBD",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"UMask": "0x1",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when PMH is busy with page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"SampleAfterValue": "100007",
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x1"
},
{
"EventCode": "0xBD",
"BriefDescription": "STLB flush attempts.",
"Counter": "0,1,2,3",
"UMask": "0x20",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"SampleAfterValue": "100007",
"BriefDescription": "STLB flush attempts.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
"UMask": "0x20"
}
]