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Merge branch 'drm-fixes-4.11' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
A few amd fixes. * 'drm-fixes-4.11' of git://people.freedesktop.org/~agd5f/linux: drm/amd/amdgpu: Fix debugfs reg read/write address width drm/amdgpu/si: add dpm quirk for Oland drm/radeon/si: add dpm quirk for Oland drm: amd: remove broken include path drm/amd/powerplay: fix copy error in smu7_clockpoweragting.c drm/amdgpu: fix parser init error path to avoid crash in parser fini drm/amd/amdgpu: Disable GFX_PG on Carrizo until compute issues solved
This commit is contained in:
commit
27b713c2e0
7 changed files with 18 additions and 6 deletions
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@ -3,6 +3,4 @@
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# of AMDSOC/AMDGPU drm driver.
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# It provides the HW control for ACP related functionalities.
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subdir-ccflags-y += -I$(AMDACPPATH)/ -I$(AMDACPPATH)/include
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AMD_ACP_FILES := $(AMDACPPATH)/acp_hw.o
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@ -240,6 +240,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
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for (; i >= 0; i--)
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drm_free_large(p->chunks[i].kdata);
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kfree(p->chunks);
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p->chunks = NULL;
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p->nchunks = 0;
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put_ctx:
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amdgpu_ctx_put(p->ctx);
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free_chunk:
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@ -2590,7 +2590,7 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
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use_bank = 0;
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}
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*pos &= 0x3FFFF;
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*pos &= (1UL << 22) - 1;
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if (use_bank) {
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if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
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@ -2666,7 +2666,7 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
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use_bank = 0;
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}
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*pos &= 0x3FFFF;
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*pos &= (1UL << 22) - 1;
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if (use_bank) {
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if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
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@ -3464,6 +3464,12 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
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(adev->pdev->device == 0x6667)) {
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max_sclk = 75000;
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}
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} else if (adev->asic_type == CHIP_OLAND) {
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if ((adev->pdev->device == 0x6604) &&
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(adev->pdev->subsystem_vendor == 0x1028) &&
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(adev->pdev->subsystem_device == 0x066F)) {
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max_sclk = 75000;
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}
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}
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if (rps->vce_active) {
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@ -1051,7 +1051,7 @@ static int vi_common_early_init(void *handle)
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/* rev0 hardware requires workarounds to support PG */
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adev->pg_flags = 0;
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if (adev->rev_id != 0x00) {
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adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
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adev->pg_flags |=
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AMD_PG_SUPPORT_GFX_SMG |
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AMD_PG_SUPPORT_GFX_PIPELINE |
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AMD_PG_SUPPORT_CP |
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@ -178,7 +178,7 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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if (bgate) {
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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AMD_PG_STATE_GATE);
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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@ -2984,6 +2984,12 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
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(rdev->pdev->device == 0x6667)) {
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max_sclk = 75000;
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}
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} else if (rdev->family == CHIP_OLAND) {
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if ((rdev->pdev->device == 0x6604) &&
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(rdev->pdev->subsystem_vendor == 0x1028) &&
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(rdev->pdev->subsystem_device == 0x066F)) {
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max_sclk = 75000;
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}
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}
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if (rps->vce_active) {
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