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PCI: Set MPS to match upstream bridge
Firmware typically configures the PCIe fabric with a consistent Max Payload Size setting based on the devices present at boot. A hot-added device typically has the power-on default MPS setting (128 bytes), which may not match the fabric. The previous Linux default, in the absence of any "pci=pcie_bus_*" options, was PCIE_BUS_TUNE_OFF, in which we never touch MPS, even for hot-added devices. Add a new default setting, PCIE_BUS_DEFAULT, in which we make sure every device's MPS setting matches the upstream bridge. This makes it more likely that a hot-added device will work in a system with optimized MPS configuration. Note that if we hot-add a device that only supports 128-byte MPS, it still likely won't work because we don't reconfigure the rest of the fabric. Booting with "pci=pcie_bus_peer2peer" is a workaround for this because it sets MPS to 128 for everything. [bhelgaas: changelog, new default, rework for pci_configure_device() path] Tested-by: Keith Busch <keith.busch@intel.com> Tested-by: Jordan Hargrave <jharg93@gmail.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org>
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4 changed files with 28 additions and 8 deletions
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@ -81,7 +81,7 @@ unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
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unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
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unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
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/*
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* The default CLS is used if arch didn't set CLS explicitly and not
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@ -1278,7 +1278,7 @@ int pci_setup_device(struct pci_dev *dev)
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static void pci_configure_mps(struct pci_dev *dev)
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{
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struct pci_dev *bridge = pci_upstream_bridge(dev);
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int mps, p_mps;
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int mps, p_mps, rc;
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if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
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return;
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@ -1294,6 +1294,23 @@ static void pci_configure_mps(struct pci_dev *dev)
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mps, pci_name(bridge), p_mps);
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return;
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}
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/*
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* Fancier MPS configuration is done later by
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* pcie_bus_configure_settings()
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*/
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if (pcie_bus_config != PCIE_BUS_DEFAULT)
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return;
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rc = pcie_set_mps(dev, p_mps);
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if (rc) {
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dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
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p_mps);
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return;
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}
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dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
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p_mps, mps, 128 << dev->pcie_mpss);
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}
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static struct hpp_type0 pci_default_type0 = {
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@ -1821,7 +1838,8 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
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if (!pci_is_pcie(dev))
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return 0;
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if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
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if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
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pcie_bus_config == PCIE_BUS_DEFAULT)
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return 0;
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mps = 128 << *(u8 *)data;
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@ -2862,7 +2862,8 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
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int err;
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u16 rcc;
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if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
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if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
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pcie_bus_config == PCIE_BUS_DEFAULT)
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return;
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/* Intel errata specifies bits to change but does not say what they are.
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@ -738,10 +738,11 @@ struct pci_driver {
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void pcie_bus_configure_settings(struct pci_bus *bus);
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enum pcie_bus_config_types {
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PCIE_BUS_TUNE_OFF,
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PCIE_BUS_SAFE,
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PCIE_BUS_PERFORMANCE,
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PCIE_BUS_PEER2PEER,
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PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
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PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
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PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
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PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
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PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
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};
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extern enum pcie_bus_config_types pcie_bus_config;
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