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Merge branch 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull shmobile clk updates from Geert Uytterhoeven: - Fix a bug in the div6 clock driver that was exposed by CAN support on R-Car H3, - Add more module clocks for R-Car H3. * 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: shmobile: r8a7795: Add CAN FD peripheral clock clk: shmobile: r8a7795: Add CANFD clock clk: shmobile: r8a7795: Add CAN peripheral clock clk: shmobile: div6: Fix .recalc_rate() using a stale divisor clk: shmobile: r8a7795: Add LVDS module clock clk: shmobile: r8a7795: Add FCP clocks
This commit is contained in:
commit
27fbd266de
2 changed files with 21 additions and 2 deletions
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@ -82,9 +82,8 @@ static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
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return parent_rate / div;
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return parent_rate / clock->div;
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}
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static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
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@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
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DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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};
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static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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@ -147,6 +148,21 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
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DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
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DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
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DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1),
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DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1),
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DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1),
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DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1),
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DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1),
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DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1),
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DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1),
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DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
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DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
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DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
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@ -164,6 +180,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
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DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
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DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A7795_CLK_S2D1),
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DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
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DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
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DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
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@ -176,6 +193,9 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
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DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
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DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
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DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
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DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
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DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
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DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
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