spi: cadence-quadspi: drop cqspi_set_protocol()
As suggested, this removes the whole cqspi_set_protocol() function, as it is not actually needed: - Checks for unsupported operations are already handled by supports_op(), removing the need to distinguish DTR and non-DTR modes in the buswidth setup - supports_op() ensures that the DTR flags match for all relevant parts of an operation, so op->cmd.dtr can be used instead of copying the flag to the cqspi_flash_pdata - The logic in cqspi_set_protocol() is moved to cqspi_calc_rdreg() and cqspi_write_setup() (with a helper macro CQSPI_OP_WIDTH()) The helper macro checks nbytes instead of buswidth for 0, for consistency with supports_op() etc. Suggested-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220420155616.281730-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Matthias Schiffer
Mark Brown
parent
2b8070840e
commit
28ac902aed
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@ -43,6 +43,8 @@
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/* Capabilities */
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#define CQSPI_SUPPORTS_OCTAL BIT(0)
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#define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0)
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struct cqspi_st;
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struct cqspi_flash_pdata {
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@ -53,10 +55,6 @@ struct cqspi_flash_pdata {
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u32 tsd2d_ns;
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u32 tchsh_ns;
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u32 tslch_ns;
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u8 inst_width;
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u8 addr_width;
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u8 data_width;
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bool dtr;
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u8 cs;
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};
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@ -343,18 +341,18 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
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return IRQ_HANDLED;
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}
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static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
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static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op)
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{
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u32 rdreg = 0;
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rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
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rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
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rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
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rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
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rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
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rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
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return rdreg;
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}
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static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
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static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
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{
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unsigned int dummy_clk;
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@ -362,66 +360,12 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
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return 0;
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dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
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if (dtr)
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if (op->cmd.dtr)
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dummy_clk /= 2;
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return dummy_clk;
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}
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static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
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const struct spi_mem_op *op)
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{
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/*
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* For an op to be DTR, cmd phase along with every other non-empty
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* phase should have dtr field set to 1. If an op phase has zero
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* nbytes, ignore its dtr field; otherwise, check its dtr field.
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*/
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f_pdata->dtr = op->cmd.dtr &&
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(!op->addr.nbytes || op->addr.dtr) &&
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(!op->data.nbytes || op->data.dtr);
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f_pdata->inst_width = 0;
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if (op->cmd.buswidth)
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f_pdata->inst_width = ilog2(op->cmd.buswidth);
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f_pdata->addr_width = 0;
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if (op->addr.buswidth)
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f_pdata->addr_width = ilog2(op->addr.buswidth);
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f_pdata->data_width = 0;
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if (op->data.buswidth)
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f_pdata->data_width = ilog2(op->data.buswidth);
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/* Right now we only support 8-8-8 DTR mode. */
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if (f_pdata->dtr) {
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switch (op->cmd.buswidth) {
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case 0:
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case 8:
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break;
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default:
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return -EINVAL;
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}
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switch (op->addr.buswidth) {
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case 0:
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case 8:
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break;
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default:
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return -EINVAL;
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}
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switch (op->data.buswidth) {
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case 0:
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case 8:
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break;
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default:
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return -EINVAL;
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}
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}
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return 0;
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}
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static int cqspi_wait_idle(struct cqspi_st *cqspi)
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{
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const unsigned int poll_idle_retry = 3;
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@ -503,8 +447,7 @@ static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
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}
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static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
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const struct spi_mem_op *op, unsigned int shift,
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bool enable)
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const struct spi_mem_op *op, unsigned int shift)
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{
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struct cqspi_st *cqspi = f_pdata->cqspi;
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void __iomem *reg_base = cqspi->iobase;
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@ -517,7 +460,7 @@ static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
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* We enable dual byte opcode here. The callers have to set up the
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* extension opcode based on which type of operation it is.
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*/
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if (enable) {
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if (op->cmd.dtr) {
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reg |= CQSPI_REG_CONFIG_DTR_PROTO;
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reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
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@ -549,12 +492,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
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size_t read_len;
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int status;
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status = cqspi_set_protocol(f_pdata, op);
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if (status)
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return status;
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status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
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f_pdata->dtr);
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status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
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if (status)
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return status;
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@ -565,17 +503,17 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
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return -EINVAL;
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}
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if (f_pdata->dtr)
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if (op->cmd.dtr)
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opcode = op->cmd.opcode >> 8;
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else
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opcode = op->cmd.opcode;
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reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
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rdreg = cqspi_calc_rdreg(f_pdata);
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rdreg = cqspi_calc_rdreg(op);
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writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
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dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
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dummy_clk = cqspi_calc_dummy(op);
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if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
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return -EOPNOTSUPP;
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@ -622,12 +560,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
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size_t write_len;
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int ret;
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ret = cqspi_set_protocol(f_pdata, op);
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if (ret)
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return ret;
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ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
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f_pdata->dtr);
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ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
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if (ret)
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return ret;
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@ -638,10 +571,10 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
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return -EINVAL;
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}
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reg = cqspi_calc_rdreg(f_pdata);
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reg = cqspi_calc_rdreg(op);
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writel(reg, reg_base + CQSPI_REG_RD_INSTR);
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if (f_pdata->dtr)
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if (op->cmd.dtr)
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opcode = op->cmd.opcode >> 8;
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else
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opcode = op->cmd.opcode;
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@ -688,21 +621,20 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
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int ret;
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u8 opcode;
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ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
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f_pdata->dtr);
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ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB);
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if (ret)
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return ret;
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if (f_pdata->dtr)
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if (op->cmd.dtr)
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opcode = op->cmd.opcode >> 8;
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else
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opcode = op->cmd.opcode;
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reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
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reg |= cqspi_calc_rdreg(f_pdata);
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reg |= cqspi_calc_rdreg(op);
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/* Setup dummy clock cycles */
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dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
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dummy_clk = cqspi_calc_dummy(op);
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if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
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return -EOPNOTSUPP;
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@ -947,22 +879,21 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
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void __iomem *reg_base = cqspi->iobase;
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u8 opcode;
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ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
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f_pdata->dtr);
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ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB);
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if (ret)
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return ret;
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if (f_pdata->dtr)
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if (op->cmd.dtr)
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opcode = op->cmd.opcode >> 8;
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else
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opcode = op->cmd.opcode;
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/* Set opcode. */
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reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
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reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
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reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
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reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
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reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
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writel(reg, reg_base + CQSPI_REG_WR_INSTR);
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reg = cqspi_calc_rdreg(f_pdata);
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reg = cqspi_calc_rdreg(op);
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writel(reg, reg_base + CQSPI_REG_RD_INSTR);
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/*
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@ -1244,10 +1175,6 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
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const u_char *buf = op->data.buf.out;
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int ret;
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ret = cqspi_set_protocol(f_pdata, op);
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if (ret)
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return ret;
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ret = cqspi_write_setup(f_pdata, op);
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if (ret)
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return ret;
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@ -1260,7 +1187,7 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
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* mode. So, we can not use direct mode when in DTR mode for writing
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* data.
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*/
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if (!f_pdata->dtr && cqspi->use_direct_mode &&
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if (!op->cmd.dtr && cqspi->use_direct_mode &&
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((to + len) <= cqspi->ahb_size)) {
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memcpy_toio(cqspi->ahb_base + to, buf, len);
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return cqspi_wait_idle(cqspi);
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@ -1348,9 +1275,6 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
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int ret;
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ddata = of_device_get_match_data(dev);
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ret = cqspi_set_protocol(f_pdata, op);
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if (ret)
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return ret;
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ret = cqspi_read_setup(f_pdata, op);
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if (ret)
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