mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-29 05:44:11 +00:00
Code Issues Releases Wiki Activity

pinctrl: qcom: lpass-lpi: split slew rate set to separate function

Browse source 
Setting slew rate for each pin will grow with upcoming Qualcomm SoCs,
so split the code responsible for this into separate function for easier
readability and maintenance.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231013145935.220945-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Krzysztof Kozlowski 2023-10-13 16:59:34 +02:00 committed by Linus Walleij
parent 22a4a9ed37
commit 28bb7c555c
1 changed files with 33 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

53
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
View file

@ -186,6 +186,35 @@ static int lpi_config_get(struct pinctrl_dev *pctldev,
return 0;
}
static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
const struct lpi_pingroup *g,
unsigned int group, unsigned int slew)
{
unsigned long sval;
int slew_offset;
if (slew > LPI_SLEW_RATE_MAX) {
dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",
slew, group);
return -EINVAL;
}
slew_offset = g->slew_offset;
if (slew_offset == LPI_NO_SLEW)
return 0;
mutex_lock(&pctrl->lock);
sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
sval |= slew << slew_offset;
iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
mutex_unlock(&pctrl->lock);
return 0;
}
static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
unsigned long *configs, unsigned int nconfs)
{
@ -193,8 +222,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
bool value, output_enabled = false;
const struct lpi_pingroup *g;
unsigned long sval;
int i, slew_offset;
int i, ret;
u32 val;
g = &pctrl->data->groups[group];
@ -226,24 +254,9 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
strength = arg;
break;
case PIN_CONFIG_SLEW_RATE:
if (arg > LPI_SLEW_RATE_MAX) {
dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
arg, group);
return -EINVAL;
}
slew_offset = g->slew_offset;
if (slew_offset == LPI_NO_SLEW)
break;
mutex_lock(&pctrl->lock);
sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
sval |= arg << slew_offset;
iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
mutex_unlock(&pctrl->lock);
ret = lpi_config_set_slew_rate(pctrl, g, group, arg);
if (ret)
return ret;
break;
default:
return -EINVAL;