mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-10-05 00:20:32 +00:00
Code Issues Releases Wiki Activity

This patch fixes setup of second EDMA channel controller

Browse source 
on DA850.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.10 (GNU/Linux)
 
 iQIcBAABAgAGBQJUBDbZAAoJEGFBu2jqvgRNS+oQAJVlvD2RbvcM+k4jt6z8t4MA
 hvxEzuZ9FsxDS8SY6YT0yVfIwp6qbUEov05mnqPybmjFeM0fezc5p31tc8TR3ezg
 i+iJMt51U3esoqll0OZ38Vbd45L2zz2cGkQC4jZoybdDI2l/hai5qAe64gGacTR1
 ee0+eRLcXARzGy52EhaG4qS8EYtJcHSwmvcFGLC65ndwuYDsHZjWgRsRXT3H5bkB
 VDQZ3LqB1uTKwK+AusXToul99Edvw/m8Nk1a0jDNQAL84dqeSKixI9aJab8i9boS
 4eUrlGmyg9Gzs1v80RulNkpBXtFSrbHDDObl6P3VS/pZnigtI9jkxNW71Lt/0jAu
 +UZkV/CEPVDvyQYnPiAPJ8AKxxawzVYY5qmgSU3O/4kxxABssj/NcB/e0BZMOfBK
 CeLKfOOrXnlAwHlrct2z9/7ukrhK7uVI0IQwGWis0RRGqAwXGMAeTyYDtuiKQDoc
 ZeYD19RhF1il4JmqOAUaLkMHmaeUFP7sL8D9xqjZ+TcBQvp93iujck4MfLMMVgD+
 YHZoHur3hUVFKUvMoeZEy1XWBENNSyvuxsnpfimy9+13fwdoZLvTD6okCMi3Kbtm
 49W0rRb2jC8StKxlhIuvapMVCnU4RyN/CsnSh9z0ug0iJ4mvXqBjtbUnVDcNrE7g
 JhgPYhgSR84IVI1dpLkc
 =Jqzz
 -----END PGP SIGNATURE-----

Merge tag 'davinci-fixes-for-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into fixes

This patch fixes setup of second EDMA channel controller
on DA850.

* tag 'davinci-fixes-for-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: edma: Fix configuration parsing for SoCs with multiple eDMA3 CC
This commit is contained in:
Arnd Bergmann 2014-09-04 21:51:05 +02:00
commit 28c2260f13
1 changed files with 5 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
arch/arm/common/edma.c
View file

@ -1443,14 +1443,14 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
EXPORT_SYMBOL(edma_assign_channel_eventq);
static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
struct edma *edma_cc)
struct edma *edma_cc, int cc_id)
{
int i;
u32 value, cccfg;
s8 (*queue_priority_map)[2];
/* Decode the eDMA3 configuration from CCCFG register */
cccfg = edma_read(0, EDMA_CCCFG);
cccfg = edma_read(cc_id, EDMA_CCCFG);
value = GET_NUM_REGN(cccfg);
edma_cc->num_region = BIT(value);
@ -1464,7 +1464,8 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
value = GET_NUM_EVQUE(cccfg);
edma_cc->num_tc = value + 1;
dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
cccfg);
dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
@ -1684,7 +1685,7 @@ static int edma_probe(struct platform_device *pdev)
return -ENOMEM;
/* Get eDMA3 configuration from IP */
ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
if (ret)
return ret;