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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMS
Replace the DRM_DEBUG with DRM_DEBUG_KMS in output device code. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
parent
44d98a6142
commit
28c97730c3
8 changed files with 99 additions and 89 deletions
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@ -159,7 +159,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
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dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
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DRM_DEBUG("Found panel mode in BIOS VBT tables:\n");
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DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
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drm_mode_debug_printmodeline(panel_fixed_mode);
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return;
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@ -250,13 +250,13 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
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u16 block_size = get_blocksize(general);
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if (block_size >= sizeof(*general)) {
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int bus_pin = general->crt_ddc_gmbus_pin;
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DRM_DEBUG("crt_ddc_bus_pin: %d\n", bus_pin);
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DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
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if ((bus_pin >= 1) && (bus_pin <= 6)) {
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dev_priv->crt_ddc_bus =
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crt_bus_map_table[bus_pin-1];
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}
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} else {
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DRM_DEBUG("BDB_GD too small (%d). Invalid.\n",
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DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
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block_size);
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}
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}
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@ -274,7 +274,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
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p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
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if (!p_defs) {
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DRM_DEBUG("No general definition block is found\n");
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DRM_DEBUG_KMS("No general definition block is found\n");
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return;
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}
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/* judge whether the size of child device meets the requirements.
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@ -284,7 +284,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
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*/
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if (p_defs->child_dev_size != sizeof(*p_child)) {
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/* different child dev size . Ignore it */
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DRM_DEBUG("different child size is found. Invalid.\n");
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DRM_DEBUG_KMS("different child size is found. Invalid.\n");
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return;
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}
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/* get the block size of general definitions */
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@ -310,10 +310,10 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
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if (p_child->dvo_port != DEVICE_PORT_DVOB &&
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p_child->dvo_port != DEVICE_PORT_DVOC) {
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/* skip the incorrect SDVO port */
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DRM_DEBUG("Incorrect SDVO port. Skip it \n");
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DRM_DEBUG_KMS("Incorrect SDVO port. Skip it \n");
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continue;
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}
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DRM_DEBUG("the SDVO device with slave addr %2x is found on "
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DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
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" %s port\n",
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p_child->slave_addr,
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(p_child->dvo_port == DEVICE_PORT_DVOB) ?
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@ -325,13 +325,13 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
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p_mapping->dvo_wiring = p_child->dvo_wiring;
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p_mapping->initialized = 1;
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} else {
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DRM_DEBUG("Maybe one SDVO port is shared by "
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DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
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"two SDVO device.\n");
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}
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if (p_child->slave2_addr) {
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/* Maybe this is a SDVO device with multiple inputs */
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/* And the mapping info is not added */
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DRM_DEBUG("there exists the slave2_addr. Maybe this "
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DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
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" is a SDVO device with multiple inputs.\n");
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}
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count++;
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@ -339,7 +339,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
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if (!count) {
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/* No SDVO device info is found */
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DRM_DEBUG("No SDVO device info is found in VBT\n");
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DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
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}
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return;
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}
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@ -194,7 +194,7 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
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ADPA_CRT_HOTPLUG_ENABLE |
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ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
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DRM_DEBUG("pch crt adpa 0x%x", adpa);
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DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
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I915_WRITE(PCH_ADPA, adpa);
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while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
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@ -994,7 +994,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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fbc_ctl |= dev_priv->cfb_fence;
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I915_WRITE(FBC_CONTROL, fbc_ctl);
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DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
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DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
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dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
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}
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@ -1017,7 +1017,7 @@ void i8xx_disable_fbc(struct drm_device *dev)
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intel_wait_for_vblank(dev);
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DRM_DEBUG("disabled FBC\n");
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DRM_DEBUG_KMS("disabled FBC\n");
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}
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static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
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@ -1062,7 +1062,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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/* enable it... */
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I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
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DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
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DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
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}
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void g4x_disable_fbc(struct drm_device *dev)
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@ -1076,7 +1076,7 @@ void g4x_disable_fbc(struct drm_device *dev)
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I915_WRITE(DPFC_CONTROL, dpfc_ctl);
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intel_wait_for_vblank(dev);
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DRM_DEBUG("disabled FBC\n");
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DRM_DEBUG_KMS("disabled FBC\n");
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}
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static bool g4x_fbc_enabled(struct drm_crtc *crtc)
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@ -1141,25 +1141,27 @@ static void intel_update_fbc(struct drm_crtc *crtc,
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* - going to an unsupported config (interlace, pixel multiply, etc.)
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*/
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if (intel_fb->obj->size > dev_priv->cfb_size) {
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DRM_DEBUG("framebuffer too large, disabling compression\n");
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DRM_DEBUG_KMS("framebuffer too large, disabling "
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"compression\n");
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goto out_disable;
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}
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if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
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(mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
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DRM_DEBUG("mode incompatible with compression, disabling\n");
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DRM_DEBUG_KMS("mode incompatible with compression, "
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"disabling\n");
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goto out_disable;
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}
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if ((mode->hdisplay > 2048) ||
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(mode->vdisplay > 1536)) {
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DRM_DEBUG("mode too large for compression, disabling\n");
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DRM_DEBUG_KMS("mode too large for compression, disabling\n");
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goto out_disable;
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}
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if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
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DRM_DEBUG("plane not 0, disabling compression\n");
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DRM_DEBUG_KMS("plane not 0, disabling compression\n");
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goto out_disable;
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}
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if (obj_priv->tiling_mode != I915_TILING_X) {
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DRM_DEBUG("framebuffer not tiled, disabling compression\n");
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DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
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goto out_disable;
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}
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@ -1181,7 +1183,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
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return;
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out_disable:
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DRM_DEBUG("unsupported config, disabling FBC\n");
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DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
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/* Multiple disables should be harmless */
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if (dev_priv->display.fbc_enabled(crtc))
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dev_priv->display.disable_fbc(dev);
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@ -1211,7 +1213,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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/* no fb bound */
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if (!crtc->fb) {
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DRM_DEBUG("No FB bound\n");
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DRM_DEBUG_KMS("No FB bound\n");
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return 0;
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}
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@ -1311,7 +1313,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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Start = obj_priv->gtt_offset;
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Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
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DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
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DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
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I915_WRITE(dspstride, crtc->fb->pitch);
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if (IS_I965G(dev)) {
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I915_WRITE(dspbase, Offset);
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@ -1385,7 +1387,7 @@ static void igdng_disable_pll_edp (struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpa_ctl;
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DRM_DEBUG("\n");
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DRM_DEBUG_KMS("\n");
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dpa_ctl = I915_READ(DP_A);
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dpa_ctl &= ~DP_PLL_ENABLE;
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I915_WRITE(DP_A, dpa_ctl);
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@ -1410,7 +1412,7 @@ static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpa_ctl;
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DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
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DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
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dpa_ctl = I915_READ(DP_A);
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dpa_ctl &= ~DP_PLL_FREQ_MASK;
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@ -1481,7 +1483,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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case DRM_MODE_DPMS_ON:
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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DRM_DEBUG("crtc %d dpms on\n", pipe);
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DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
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if (HAS_eDP) {
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/* enable eDP PLL */
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igdng_enable_pll_edp(crtc);
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@ -1568,12 +1570,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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udelay(150);
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temp = I915_READ(fdi_rx_iir_reg);
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DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
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DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
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if ((temp & FDI_RX_BIT_LOCK) == 0) {
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for (j = 0; j < tries; j++) {
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temp = I915_READ(fdi_rx_iir_reg);
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DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
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DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
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temp);
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if (temp & FDI_RX_BIT_LOCK)
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break;
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udelay(200);
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@ -1582,11 +1585,11 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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I915_WRITE(fdi_rx_iir_reg,
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temp | FDI_RX_BIT_LOCK);
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else
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DRM_DEBUG("train 1 fail\n");
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DRM_DEBUG_KMS("train 1 fail\n");
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} else {
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I915_WRITE(fdi_rx_iir_reg,
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temp | FDI_RX_BIT_LOCK);
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DRM_DEBUG("train 1 ok 2!\n");
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DRM_DEBUG_KMS("train 1 ok 2!\n");
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}
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temp = I915_READ(fdi_tx_reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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@ -1601,12 +1604,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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udelay(150);
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temp = I915_READ(fdi_rx_iir_reg);
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DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
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DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
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if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
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for (j = 0; j < tries; j++) {
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temp = I915_READ(fdi_rx_iir_reg);
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DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
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DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
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temp);
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if (temp & FDI_RX_SYMBOL_LOCK)
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break;
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udelay(200);
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@ -1614,15 +1618,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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if (j != tries) {
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I915_WRITE(fdi_rx_iir_reg,
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temp | FDI_RX_SYMBOL_LOCK);
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DRM_DEBUG("train 2 ok 1!\n");
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DRM_DEBUG_KMS("train 2 ok 1!\n");
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} else
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DRM_DEBUG("train 2 fail\n");
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DRM_DEBUG_KMS("train 2 fail\n");
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} else {
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I915_WRITE(fdi_rx_iir_reg,
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temp | FDI_RX_SYMBOL_LOCK);
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DRM_DEBUG("train 2 ok 2!\n");
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DRM_DEBUG_KMS("train 2 ok 2!\n");
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}
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DRM_DEBUG("train done\n");
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DRM_DEBUG_KMS("train done\n");
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/* set transcoder timing */
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I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
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@ -1664,7 +1668,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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break;
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case DRM_MODE_DPMS_OFF:
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DRM_DEBUG("crtc %d dpms off\n", pipe);
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DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
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i915_disable_vga(dev);
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@ -1690,12 +1694,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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udelay(500);
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continue;
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} else {
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DRM_DEBUG("pipe %d off delay\n", pipe);
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DRM_DEBUG_KMS("pipe %d off delay\n",
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pipe);
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break;
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}
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}
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} else
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DRM_DEBUG("crtc %d is disabled\n", pipe);
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DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
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if (HAS_eDP) {
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igdng_disable_pll_edp(crtc);
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@ -1738,7 +1743,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
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udelay(500);
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continue;
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} else {
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DRM_DEBUG("transcoder %d off delay\n", pipe);
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DRM_DEBUG_KMS("transcoder %d off "
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"delay\n", pipe);
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break;
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}
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}
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@ -2245,11 +2251,11 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
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1000;
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entries_required /= wm->cacheline_size;
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DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
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DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
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wm_size = wm->fifo_size - (entries_required + wm->guard_size);
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DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
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DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
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/* Don't promote wm_size to unsigned... */
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if (wm_size > (long)wm->max_wm)
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@ -2311,7 +2317,7 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
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return latency;
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}
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DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
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DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
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return NULL;
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}
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@ -2339,7 +2345,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
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latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
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dev_priv->mem_freq);
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if (!latency) {
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DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
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DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
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igd_disable_cxsr(dev);
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return;
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}
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@ -2351,7 +2357,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
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reg &= 0x7fffff;
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reg |= wm << 23;
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I915_WRITE(DSPFW1, reg);
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DRM_DEBUG("DSPFW1 register is %x\n", reg);
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DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
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/* cursor SR */
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wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
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@ -2376,7 +2382,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
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reg &= ~(0x3f << 16);
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reg |= (wm & 0x3f) << 16;
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I915_WRITE(DSPFW3, reg);
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DRM_DEBUG("DSPFW3 register is %x\n", reg);
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DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
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/* activate cxsr */
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reg = I915_READ(DSPFW3);
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@ -2416,8 +2422,8 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
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size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
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(dsparb & 0x7f);
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DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
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size);
|
||||
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
|
||||
plane ? "B" : "A", size);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
@ -2435,8 +2441,8 @@ static int i85x_get_fifo_size(struct drm_device *dev, int plane)
|
|||
(dsparb & 0x1ff);
|
||||
size >>= 1; /* Convert to cachelines */
|
||||
|
||||
DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
|
||||
size);
|
||||
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
|
||||
plane ? "B" : "A", size);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
@ -2450,7 +2456,8 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
|
|||
size = dsparb & 0x7f;
|
||||
size >>= 2; /* Convert to cachelines */
|
||||
|
||||
DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
|
||||
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
|
||||
plane ? "B" : "A",
|
||||
size);
|
||||
|
||||
return size;
|
||||
|
@ -2465,8 +2472,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
|
|||
size = dsparb & 0x7f;
|
||||
size >>= 1; /* Convert to cachelines */
|
||||
|
||||
DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
|
||||
size);
|
||||
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
|
||||
plane ? "B" : "A", size);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
@ -2546,7 +2553,7 @@ static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
|
|||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
|
||||
DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
|
||||
|
||||
/* 965 has limitations... */
|
||||
I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
|
||||
|
@ -2585,7 +2592,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
|
|||
pixel_size, latency_ns);
|
||||
planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
|
||||
pixel_size, latency_ns);
|
||||
DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
|
||||
DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
|
||||
|
||||
/*
|
||||
* Overlay gets an aggressive default since video jitter is bad.
|
||||
|
@ -2605,14 +2612,14 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
|
|||
sr_entries = (((sr_latency_ns / line_time_us) + 1) *
|
||||
pixel_size * sr_hdisplay) / 1000;
|
||||
sr_entries = roundup(sr_entries / cacheline_size, 1);
|
||||
DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
|
||||
DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
|
||||
srwm = total_size - sr_entries;
|
||||
if (srwm < 0)
|
||||
srwm = 1;
|
||||
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
|
||||
}
|
||||
|
||||
DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
|
||||
DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
|
||||
planea_wm, planeb_wm, cwm, srwm);
|
||||
|
||||
fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
|
||||
|
@ -2639,7 +2646,7 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
|
|||
pixel_size, latency_ns);
|
||||
fwater_lo |= (3<<8) | planea_wm;
|
||||
|
||||
DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
|
||||
DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
|
||||
|
||||
I915_WRITE(FW_BLC, fwater_lo);
|
||||
}
|
||||
|
@ -2693,11 +2700,11 @@ static void intel_update_watermarks(struct drm_device *dev)
|
|||
if (crtc->enabled) {
|
||||
enabled++;
|
||||
if (intel_crtc->plane == 0) {
|
||||
DRM_DEBUG("plane A (pipe %d) clock: %d\n",
|
||||
DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
|
||||
intel_crtc->pipe, crtc->mode.clock);
|
||||
planea_clock = crtc->mode.clock;
|
||||
} else {
|
||||
DRM_DEBUG("plane B (pipe %d) clock: %d\n",
|
||||
DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
|
||||
intel_crtc->pipe, crtc->mode.clock);
|
||||
planeb_clock = crtc->mode.clock;
|
||||
}
|
||||
|
@ -2811,7 +2818,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
|
||||
if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
|
||||
refclk = dev_priv->lvds_ssc_freq * 1000;
|
||||
DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
|
||||
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
|
||||
refclk / 1000);
|
||||
} else if (IS_I9XX(dev)) {
|
||||
refclk = 96000;
|
||||
if (IS_IGDNG(dev))
|
||||
|
@ -3069,7 +3077,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
|
||||
I915_WRITE(PFIT_CONTROL, 0);
|
||||
|
||||
DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
|
||||
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
|
||||
drm_mode_debug_printmodeline(mode);
|
||||
|
||||
/* assign to IGDNG registers */
|
||||
|
@ -3147,14 +3155,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
I915_WRITE(fp_reg + 4, fp2);
|
||||
intel_crtc->lowfreq_avail = true;
|
||||
if (HAS_PIPE_CXSR(dev)) {
|
||||
DRM_DEBUG("enabling CxSR downclocking\n");
|
||||
DRM_DEBUG_KMS("enabling CxSR downclocking\n");
|
||||
pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
|
||||
}
|
||||
} else {
|
||||
I915_WRITE(fp_reg + 4, fp);
|
||||
intel_crtc->lowfreq_avail = false;
|
||||
if (HAS_PIPE_CXSR(dev)) {
|
||||
DRM_DEBUG("disabling CxSR downclocking\n");
|
||||
DRM_DEBUG_KMS("disabling CxSR downclocking\n");
|
||||
pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
|
||||
}
|
||||
}
|
||||
|
@ -3266,11 +3274,11 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
|
|||
size_t addr;
|
||||
int ret;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
/* if we want to turn off the cursor ignore width and height */
|
||||
if (!handle) {
|
||||
DRM_DEBUG("cursor off\n");
|
||||
DRM_DEBUG_KMS("cursor off\n");
|
||||
if (IS_MOBILE(dev) || IS_I9XX(dev)) {
|
||||
temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
|
||||
temp |= CURSOR_MODE_DISABLE;
|
||||
|
@ -3604,7 +3612,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
|
|||
7 : 14;
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unknown DPLL mode %08x in programmed "
|
||||
DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
|
||||
"mode\n", (int)(dpll & DPLL_MODE_MASK));
|
||||
return 0;
|
||||
}
|
||||
|
@ -4042,7 +4050,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
|
|||
intel_crtc->pipe = pipe;
|
||||
intel_crtc->plane = pipe;
|
||||
if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
|
||||
DRM_DEBUG("swapping pipes & planes for FBC\n");
|
||||
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
|
||||
intel_crtc->plane = ((pipe == 0) ? 1 : 0);
|
||||
}
|
||||
|
||||
|
@ -4471,7 +4479,7 @@ void intel_modeset_init(struct drm_device *dev)
|
|||
num_pipe = 2;
|
||||
else
|
||||
num_pipe = 1;
|
||||
DRM_DEBUG("%d display pipe%s available.\n",
|
||||
DRM_DEBUG_KMS("%d display pipe%s available.\n",
|
||||
num_pipe, num_pipe > 1 ? "s" : "");
|
||||
|
||||
if (IS_I85X(dev))
|
||||
|
|
|
@ -282,7 +282,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
|
|||
/* Timeouts occur when the device isn't connected, so they're
|
||||
* "normal" -- don't fill the kernel log with these */
|
||||
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
|
||||
DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status);
|
||||
DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
|
@ -435,7 +435,8 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
|
|||
dp_priv->link_bw = bws[clock];
|
||||
dp_priv->lane_count = lane_count;
|
||||
adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
|
||||
DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n",
|
||||
DRM_DEBUG_KMS("Display port link bw %02x lane "
|
||||
"count %d clock %d\n",
|
||||
dp_priv->link_bw, dp_priv->lane_count,
|
||||
adjusted_mode->clock);
|
||||
return true;
|
||||
|
@ -611,7 +612,7 @@ static void igdng_edp_backlight_on (struct drm_device *dev)
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
u32 pp;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
DRM_DEBUG_KMS("\n");
|
||||
pp = I915_READ(PCH_PP_CONTROL);
|
||||
pp |= EDP_BLC_ENABLE;
|
||||
I915_WRITE(PCH_PP_CONTROL, pp);
|
||||
|
@ -622,7 +623,7 @@ static void igdng_edp_backlight_off (struct drm_device *dev)
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
u32 pp;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
DRM_DEBUG_KMS("\n");
|
||||
pp = I915_READ(PCH_PP_CONTROL);
|
||||
pp &= ~EDP_BLC_ENABLE;
|
||||
I915_WRITE(PCH_PP_CONTROL, pp);
|
||||
|
@ -1010,7 +1011,7 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_dp_priv *dp_priv = intel_output->dev_priv;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
if (IS_eDP(intel_output)) {
|
||||
DP &= ~DP_PLL_ENABLE;
|
||||
|
|
|
@ -85,7 +85,7 @@ i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
|
|||
msg, msg_bytes,
|
||||
reply, reply_bytes);
|
||||
if (ret < 0) {
|
||||
DRM_DEBUG("aux_ch failed %d\n", ret);
|
||||
DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
switch (reply[0] & AUX_I2C_REPLY_MASK) {
|
||||
|
@ -95,10 +95,10 @@ i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
|
|||
}
|
||||
return reply_bytes - 1;
|
||||
case AUX_I2C_REPLY_NACK:
|
||||
DRM_DEBUG("aux_ch nack\n");
|
||||
DRM_DEBUG_KMS("aux_ch nack\n");
|
||||
return -EREMOTEIO;
|
||||
case AUX_I2C_REPLY_DEFER:
|
||||
DRM_DEBUG("aux_ch defer\n");
|
||||
DRM_DEBUG_KMS("aux_ch defer\n");
|
||||
udelay(100);
|
||||
break;
|
||||
default:
|
||||
|
@ -224,7 +224,7 @@ i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
|
|||
if (ret >= 0)
|
||||
ret = num;
|
||||
i2c_algo_dp_aux_stop(adapter, reading);
|
||||
DRM_DEBUG("dp_aux_xfer return %d\n", ret);
|
||||
DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -230,8 +230,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
|
|||
par->intel_fb = intel_fb;
|
||||
|
||||
/* To allow resizeing without swapping buffers */
|
||||
DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width,
|
||||
intel_fb->base.height, obj_priv->gtt_offset, fbo);
|
||||
DRM_DEBUG_KMS("allocated %dx%d fb: 0x%08x, bo %p\n",
|
||||
intel_fb->base.width, intel_fb->base.height,
|
||||
obj_priv->gtt_offset, fbo);
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
return 0;
|
||||
|
@ -249,7 +250,7 @@ int intelfb_probe(struct drm_device *dev)
|
|||
{
|
||||
int ret;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
DRM_DEBUG_KMS("\n");
|
||||
ret = drm_fb_helper_single_fb_probe(dev, 32, intelfb_create);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -950,7 +950,7 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
|
||||
return;
|
||||
if (dev_priv->edp_support) {
|
||||
DRM_DEBUG("disable LVDS for eDP support\n");
|
||||
DRM_DEBUG_KMS("disable LVDS for eDP support\n");
|
||||
return;
|
||||
}
|
||||
gpio = PCH_GPIOC;
|
||||
|
@ -1082,7 +1082,7 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
}
|
||||
dev_priv->lid_notifier.notifier_call = intel_lid_notify;
|
||||
if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
|
||||
DRM_DEBUG("lid notifier registration failed\n");
|
||||
DRM_DEBUG_KMS("lid notifier registration failed\n");
|
||||
dev_priv->lid_notifier.notifier_call = NULL;
|
||||
}
|
||||
drm_sysfs_connector_add(connector);
|
||||
|
|
|
@ -1416,16 +1416,16 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
|
|||
* 0 0 0 Component
|
||||
*/
|
||||
if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
|
||||
DRM_DEBUG("Detected Composite TV connection\n");
|
||||
DRM_DEBUG_KMS("Detected Composite TV connection\n");
|
||||
type = DRM_MODE_CONNECTOR_Composite;
|
||||
} else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
|
||||
DRM_DEBUG("Detected S-Video TV connection\n");
|
||||
DRM_DEBUG_KMS("Detected S-Video TV connection\n");
|
||||
type = DRM_MODE_CONNECTOR_SVIDEO;
|
||||
} else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
|
||||
DRM_DEBUG("Detected Component TV connection\n");
|
||||
DRM_DEBUG_KMS("Detected Component TV connection\n");
|
||||
type = DRM_MODE_CONNECTOR_Component;
|
||||
} else {
|
||||
DRM_DEBUG("No TV connection detected\n");
|
||||
DRM_DEBUG_KMS("No TV connection detected\n");
|
||||
type = -1;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue