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drm/i915/display/vlv: use intel_de_rmw if possible
The helper makes the code more compact and readable. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221219092428.2515430-2-andrzej.hajda@intel.com
This commit is contained in:
parent
fceeca7f3c
commit
28cbe92b59
2 changed files with 40 additions and 108 deletions
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@ -331,32 +331,23 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 tmp;
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bool cold_boot = false;
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/* Set the MIPI mode
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* If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
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* Power ON MIPI IO first and then write into IO reset and LP wake bits
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*/
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
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intel_de_write(dev_priv, MIPI_CTRL(port),
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tmp | GLK_MIPIIO_ENABLE);
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}
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for_each_dsi_port(port, intel_dsi->ports)
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intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE);
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/* Put the IO into reset */
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tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
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tmp &= ~GLK_MIPIIO_RESET_RELEASED;
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intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
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intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
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/* Program LP Wake */
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
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if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
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tmp &= ~GLK_LP_WAKE;
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else
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tmp |= GLK_LP_WAKE;
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intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
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u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
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intel_de_rmw(dev_priv, MIPI_CTRL(port),
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GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
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}
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/* Wait for Pwr ACK */
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@ -380,7 +371,6 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 val;
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/* Wait for MIPI PHY status bit to set */
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for_each_dsi_port(port, intel_dsi->ports) {
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@ -390,24 +380,18 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
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}
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/* Get IO out of reset */
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val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
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intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
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val | GLK_MIPIIO_RESET_RELEASED);
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intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
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/* Get IO out of Low power state*/
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for_each_dsi_port(port, intel_dsi->ports) {
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if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
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val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= DEVICE_READY;
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
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intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
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ULPS_STATE_MASK, DEVICE_READY);
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usleep_range(10, 15);
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} else {
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/* Enter ULPS */
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val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_ENTER | DEVICE_READY);
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
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intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
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ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
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/* Wait for ULPS active */
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if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
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@ -415,20 +399,15 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
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drm_err(&dev_priv->drm, "ULPS not active\n");
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/* Exit ULPS */
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val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_EXIT | DEVICE_READY);
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
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intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
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ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
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/* Enter Normal Mode */
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val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
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intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
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ULPS_STATE_MASK,
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ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
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val = intel_de_read(dev_priv, MIPI_CTRL(port));
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val &= ~GLK_LP_WAKE;
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intel_de_write(dev_priv, MIPI_CTRL(port), val);
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intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0);
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}
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}
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@ -460,9 +439,7 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder)
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/* Enable MIPI PHY transparent latch */
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for_each_dsi_port(port, intel_dsi->ports) {
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val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
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intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port),
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val | LP_OUTPUT_HOLD);
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intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
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usleep_range(2000, 2500);
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}
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@ -482,7 +459,6 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 val;
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drm_dbg_kms(&dev_priv->drm, "\n");
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@ -505,9 +481,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
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* Common bit for both MIPI Port A & MIPI Port C
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* No similar bit in MIPI Port C reg
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*/
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val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A));
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intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A),
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val | LP_OUTPUT_HOLD);
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intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
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usleep_range(1000, 1500);
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
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@ -537,15 +511,11 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 val;
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/* Enter ULPS */
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for_each_dsi_port(port, intel_dsi->ports) {
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val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_ENTER | DEVICE_READY);
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
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}
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for_each_dsi_port(port, intel_dsi->ports)
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intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
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ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
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/* Wait for MIPI PHY status bit to unset */
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for_each_dsi_port(port, intel_dsi->ports) {
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@ -568,12 +538,9 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 tmp;
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/* Put the IO into reset */
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tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
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tmp &= ~GLK_MIPIIO_RESET_RELEASED;
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intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
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intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
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/* Wait for MIPI PHY status bit to unset */
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for_each_dsi_port(port, intel_dsi->ports) {
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@ -583,11 +550,8 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
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}
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/* Clear MIPI mode */
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
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tmp &= ~GLK_MIPIIO_ENABLE;
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intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
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}
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for_each_dsi_port(port, intel_dsi->ports)
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intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0);
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}
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static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
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@ -607,7 +571,6 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
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/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
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i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
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BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
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u32 val;
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
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DEVICE_READY | ULPS_STATE_ENTER);
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@ -631,8 +594,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
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drm_err(&dev_priv->drm, "DSI LP not going Low\n");
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/* Disable MIPI PHY transparent latch */
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val = intel_de_read(dev_priv, port_ctrl);
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intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD);
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intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0);
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usleep_range(1000, 1500);
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
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@ -703,11 +665,9 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
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for_each_dsi_port(port, intel_dsi->ports) {
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i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
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BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
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u32 temp;
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/* de-assert ip_tg_enable signal */
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temp = intel_de_read(dev_priv, port_ctrl);
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intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE);
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intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0);
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intel_de_posting_read(dev_priv, port_ctrl);
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}
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}
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@ -781,7 +741,6 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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enum port port;
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u32 val;
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bool glk_cold_boot = false;
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drm_dbg_kms(&dev_priv->drm, "\n");
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@ -804,9 +763,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
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if (IS_BROXTON(dev_priv)) {
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/* Add MIPI IO reset programming for modeset */
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val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
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intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
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val | MIPIO_RST_CTRL);
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intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
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/* Power up DSI regulator */
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intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
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@ -814,12 +771,9 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
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}
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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u32 val;
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/* Disable DPOunit clock gating, can stall pipe */
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val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
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val |= DPOUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
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intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
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0, DPOUNIT_CLOCK_GATE_DISABLE);
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}
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if (!IS_GEMINILAKE(dev_priv))
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@ -943,7 +897,6 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 val;
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drm_dbg_kms(&dev_priv->drm, "\n");
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@ -981,21 +934,16 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
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HS_IO_CTRL_SELECT);
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/* Add MIPI IO reset programming for modeset */
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val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
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intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
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val & ~MIPIO_RST_CTRL);
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intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
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}
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if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
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bxt_dsi_pll_disable(encoder);
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} else {
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u32 val;
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vlv_dsi_pll_disable(encoder);
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val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
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val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
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intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
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DPOUNIT_CLOCK_GATE_DISABLE, 0);
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}
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/* Assert reset */
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@ -1426,11 +1374,8 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
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} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
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enum pipe pipe = crtc->pipe;
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tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
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tmp &= ~BXT_PIPE_SELECT_MASK;
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tmp |= BXT_PIPE_SELECT(pipe);
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intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
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intel_de_rmw(dev_priv, MIPI_CTRL(port),
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BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
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}
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/* XXX: why here, why like this? handling in irq handler?! */
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@ -1599,7 +1544,6 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 val;
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if (IS_GEMINILAKE(dev_priv))
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return;
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@ -1614,9 +1558,7 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
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vlv_dsi_reset_clocks(encoder, port);
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intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
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val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port));
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val &= ~VID_MODE_FORMAT_MASK;
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intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
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intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0);
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intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
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}
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@ -302,13 +302,10 @@ bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
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void bxt_dsi_pll_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 val;
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drm_dbg_kms(&dev_priv->drm, "\n");
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val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
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val &= ~BXT_DSI_PLL_DO_ENABLE;
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intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val);
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intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0);
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/*
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* PLL lock should deassert within 200us.
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@ -542,7 +539,6 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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u32 val;
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drm_dbg_kms(&dev_priv->drm, "\n");
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@ -559,9 +555,7 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder,
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}
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/* Enable DSI PLL */
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val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
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val |= BXT_DSI_PLL_DO_ENABLE;
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intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val);
|
||||
intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);
|
||||
|
||||
/* Timeout and fail if PLL not locked */
|
||||
if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE,
|
||||
|
@ -589,13 +583,9 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
|
|||
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
|
||||
intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);
|
||||
} else {
|
||||
tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1);
|
||||
tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
|
||||
intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp);
|
||||
intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);
|
||||
|
||||
tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2);
|
||||
tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
|
||||
intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp);
|
||||
intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);
|
||||
}
|
||||
intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue