spi: uniphier: Add DMA transfer mode support
This adds DMA transfer mode support for UniPhier SPI controller. Since this controller requires simulteaneous transmission and reception, this indicates SPI_CONTROLLER_MUST_RX and SPI_CONTROLLER_MUST_TX. Because the supported dma controller has alignment restiction, there is also a restriction that 'maxburst' parameters in dma_slave_config corresponds to one word width. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1577149107-30670-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kunihiko Hayashi
Mark Brown
parent
790514ed77
commit
28d1dddc59
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@ -8,6 +8,7 @@
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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@ -23,6 +24,7 @@
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struct uniphier_spi_priv {
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void __iomem *base;
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dma_addr_t base_dma_addr;
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struct clk *clk;
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struct spi_master *master;
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struct completion xfer_done;
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@ -32,6 +34,7 @@ struct uniphier_spi_priv {
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unsigned int rx_bytes;
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const u8 *tx_buf;
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u8 *rx_buf;
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atomic_t dma_busy;
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bool is_save_param;
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u8 bits_per_word;
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@ -61,11 +64,16 @@ struct uniphier_spi_priv {
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#define SSI_FPS_FSTRT BIT(14)
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#define SSI_SR 0x14
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#define SSI_SR_BUSY BIT(7)
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#define SSI_SR_RNE BIT(0)
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#define SSI_IE 0x18
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#define SSI_IE_TCIE BIT(4)
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#define SSI_IE_RCIE BIT(3)
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#define SSI_IE_TXRE BIT(2)
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#define SSI_IE_RXRE BIT(1)
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#define SSI_IE_RORIE BIT(0)
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#define SSI_IE_ALL_MASK GENMASK(4, 0)
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#define SSI_IS 0x1c
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#define SSI_IS_RXRS BIT(9)
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@ -87,6 +95,10 @@ struct uniphier_spi_priv {
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#define SSI_RXDR 0x24
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#define SSI_FIFO_DEPTH 8U
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#define SSI_FIFO_BURST_NUM 1
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#define SSI_DMA_RX_BUSY BIT(1)
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#define SSI_DMA_TX_BUSY BIT(0)
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static inline unsigned int bytes_per_word(unsigned int bits)
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{
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@ -334,6 +346,128 @@ static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
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writel(val, priv->base + SSI_FPS);
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}
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static bool uniphier_spi_can_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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unsigned int bpw = bytes_per_word(priv->bits_per_word);
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if ((!master->dma_tx && !master->dma_rx)
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|| (!master->dma_tx && t->tx_buf)
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|| (!master->dma_rx && t->rx_buf))
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return false;
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return DIV_ROUND_UP(t->len, bpw) > SSI_FIFO_DEPTH;
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}
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static void uniphier_spi_dma_rxcb(void *data)
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{
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struct spi_master *master = data;
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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int state = atomic_fetch_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
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uniphier_spi_irq_disable(priv, SSI_IE_RXRE);
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if (!(state & SSI_DMA_TX_BUSY))
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spi_finalize_current_transfer(master);
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}
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static void uniphier_spi_dma_txcb(void *data)
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{
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struct spi_master *master = data;
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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int state = atomic_fetch_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
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uniphier_spi_irq_disable(priv, SSI_IE_TXRE);
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if (!(state & SSI_DMA_RX_BUSY))
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spi_finalize_current_transfer(master);
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}
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static int uniphier_spi_transfer_one_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
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int buswidth;
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atomic_set(&priv->dma_busy, 0);
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uniphier_spi_set_fifo_threshold(priv, SSI_FIFO_BURST_NUM);
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if (priv->bits_per_word <= 8)
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buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
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else if (priv->bits_per_word <= 16)
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buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
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else
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buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
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if (priv->rx_buf) {
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struct dma_slave_config rxconf = {
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.direction = DMA_DEV_TO_MEM,
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.src_addr = priv->base_dma_addr + SSI_RXDR,
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.src_addr_width = buswidth,
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.src_maxburst = SSI_FIFO_BURST_NUM,
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};
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dmaengine_slave_config(master->dma_rx, &rxconf);
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rxdesc = dmaengine_prep_slave_sg(
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master->dma_rx,
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t->rx_sg.sgl, t->rx_sg.nents,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!rxdesc)
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goto out_err_prep;
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rxdesc->callback = uniphier_spi_dma_rxcb;
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rxdesc->callback_param = master;
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uniphier_spi_irq_enable(priv, SSI_IE_RXRE);
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atomic_or(SSI_DMA_RX_BUSY, &priv->dma_busy);
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dmaengine_submit(rxdesc);
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dma_async_issue_pending(master->dma_rx);
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}
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if (priv->tx_buf) {
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struct dma_slave_config txconf = {
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.direction = DMA_MEM_TO_DEV,
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.dst_addr = priv->base_dma_addr + SSI_TXDR,
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.dst_addr_width = buswidth,
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.dst_maxburst = SSI_FIFO_BURST_NUM,
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};
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dmaengine_slave_config(master->dma_tx, &txconf);
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txdesc = dmaengine_prep_slave_sg(
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master->dma_tx,
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t->tx_sg.sgl, t->tx_sg.nents,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc)
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goto out_err_prep;
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txdesc->callback = uniphier_spi_dma_txcb;
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txdesc->callback_param = master;
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uniphier_spi_irq_enable(priv, SSI_IE_TXRE);
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atomic_or(SSI_DMA_TX_BUSY, &priv->dma_busy);
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dmaengine_submit(txdesc);
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dma_async_issue_pending(master->dma_tx);
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}
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/* signal that we need to wait for completion */
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return (priv->tx_buf || priv->rx_buf);
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out_err_prep:
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if (rxdesc)
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dmaengine_terminate_sync(master->dma_rx);
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return -EINVAL;
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}
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static int uniphier_spi_transfer_one_irq(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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@ -395,6 +529,7 @@ static int uniphier_spi_transfer_one(struct spi_master *master,
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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unsigned long threshold;
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bool use_dma;
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/* Terminate and return success for 0 byte length transfer */
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if (!t->len)
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@ -402,6 +537,10 @@ static int uniphier_spi_transfer_one(struct spi_master *master,
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uniphier_spi_setup_transfer(spi, t);
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use_dma = master->can_dma ? master->can_dma(master, spi, t) : false;
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if (use_dma)
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return uniphier_spi_transfer_one_dma(master, spi, t);
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/*
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* If the transfer operation will take longer than
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* SSI_POLL_TIMEOUT_US, it should use irq.
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@ -445,7 +584,17 @@ static void uniphier_spi_handle_err(struct spi_master *master,
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val = SSI_FC_TXFFL | SSI_FC_RXFFL;
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writel(val, priv->base + SSI_FC);
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uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
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uniphier_spi_irq_disable(priv, SSI_IE_ALL_MASK);
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if (atomic_read(&priv->dma_busy) & SSI_DMA_TX_BUSY) {
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dmaengine_terminate_async(master->dma_tx);
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atomic_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
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}
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if (atomic_read(&priv->dma_busy) & SSI_DMA_RX_BUSY) {
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dmaengine_terminate_async(master->dma_rx);
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atomic_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
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}
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}
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static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
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@ -493,6 +642,9 @@ static int uniphier_spi_probe(struct platform_device *pdev)
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{
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struct uniphier_spi_priv *priv;
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struct spi_master *master;
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struct resource *res;
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struct dma_slave_caps caps;
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u32 dma_tx_burst = 0, dma_rx_burst = 0;
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unsigned long clk_rate;
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int irq;
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int ret;
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@ -507,11 +659,13 @@ static int uniphier_spi_probe(struct platform_device *pdev)
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priv->master = master;
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priv->is_save_param = false;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->base)) {
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ret = PTR_ERR(priv->base);
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goto out_master_put;
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}
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priv->base_dma_addr = res->start;
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priv->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(priv->clk)) {
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@ -555,7 +709,44 @@ static int uniphier_spi_probe(struct platform_device *pdev)
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master->unprepare_transfer_hardware
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= uniphier_spi_unprepare_transfer_hardware;
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master->handle_err = uniphier_spi_handle_err;
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master->can_dma = uniphier_spi_can_dma;
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master->num_chipselect = 1;
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master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
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master->dma_tx = dma_request_chan(&pdev->dev, "tx");
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if (IS_ERR_OR_NULL(master->dma_tx)) {
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if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER)
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goto out_disable_clk;
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master->dma_tx = NULL;
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dma_tx_burst = INT_MAX;
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} else {
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ret = dma_get_slave_caps(master->dma_tx, &caps);
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if (ret) {
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dev_err(&pdev->dev, "failed to get TX DMA capacities: %d\n",
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ret);
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goto out_disable_clk;
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}
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dma_tx_burst = caps.max_burst;
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}
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master->dma_rx = dma_request_chan(&pdev->dev, "rx");
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if (IS_ERR_OR_NULL(master->dma_rx)) {
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if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER)
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goto out_disable_clk;
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master->dma_rx = NULL;
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dma_rx_burst = INT_MAX;
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} else {
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ret = dma_get_slave_caps(master->dma_rx, &caps);
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if (ret) {
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dev_err(&pdev->dev, "failed to get RX DMA capacities: %d\n",
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ret);
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goto out_disable_clk;
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}
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dma_rx_burst = caps.max_burst;
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}
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master->max_dma_len = min(dma_tx_burst, dma_rx_burst);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret)
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@ -575,6 +766,11 @@ static int uniphier_spi_remove(struct platform_device *pdev)
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{
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struct uniphier_spi_priv *priv = platform_get_drvdata(pdev);
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if (priv->master->dma_tx)
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dma_release_channel(priv->master->dma_tx);
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if (priv->master->dma_rx)
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dma_release_channel(priv->master->dma_rx);
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clk_disable_unprepare(priv->clk);
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return 0;
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