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dmaengine: ste_dma40: Move default memcpy configs into the driver
There are only two default memcpy configurations used for the DMA40 driver; one for physical memcpy and one for logical memcpy. Instead of invariably passing the same configurations though platform data, we're moving them into the driver instead. Acked-by: Vinod Koul <vnod.koul@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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parent
a2acaa2163
commit
29027a1e11
3 changed files with 30 additions and 34 deletions
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@ -42,32 +42,6 @@ static struct resource dma40_resources[] = {
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}
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};
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/* Default configuration for physcial memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
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.mode = STEDMA40_MODE_PHYSICAL,
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_PHY_1,
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.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_PHY_1,
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.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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};
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/* Default configuration for logical memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_log = {
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_LOG_1,
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.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_LOG_1,
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.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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};
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/*
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* Mapping between destination event lines and physical device address.
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* The event line is tied to a device and therefore the address is constant.
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@ -150,8 +124,6 @@ static struct stedma40_platform_data dma40_plat_data = {
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.dev_len = DB8500_DMA_NR_DEV,
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.dev_rx = dma40_rx_map,
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.dev_tx = dma40_tx_map,
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.memcpy_conf_phy = &dma40_memcpy_conf_phy,
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.memcpy_conf_log = &dma40_memcpy_conf_log,
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.disabled_channels = {-1},
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};
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@ -72,6 +72,34 @@ static int dma40_memcpy_channels[] = {
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DB8500_DMA_MEMCPY_EV_5,
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};
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/* Default configuration for physcial memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
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.mode = STEDMA40_MODE_PHYSICAL,
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_PHY_1,
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.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_PHY_1,
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.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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};
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/* Default configuration for logical memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_log = {
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.mode = STEDMA40_MODE_LOGICAL,
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_LOG_1,
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.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_LOG_1,
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.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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};
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/**
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* enum 40_command - The different commands and/or statuses.
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*
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@ -2029,13 +2057,13 @@ static int d40_config_memcpy(struct d40_chan *d40c)
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dma_cap_mask_t cap = d40c->chan.device->cap_mask;
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if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
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d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
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d40c->dma_cfg = dma40_memcpy_conf_log;
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d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
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d40c->dma_cfg.dst_dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
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} else if (dma_has_cap(DMA_MEMCPY, cap) &&
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dma_has_cap(DMA_SLAVE, cap)) {
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d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
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d40c->dma_cfg = dma40_memcpy_conf_phy;
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} else {
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chan_err(d40c, "No memcpy\n");
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return -EINVAL;
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@ -141,8 +141,6 @@ struct stedma40_chan_cfg {
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* @dev_len: length of dev_tx and dev_rx
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* @dev_tx: mapping between destination event line and io address
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* @dev_rx: mapping between source event line and io address
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* @memcpy_conf_phy: default configuration of physical channel memcpy
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* @memcpy_conf_log: default configuration of logical channel memcpy
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* @disabled_channels: A vector, ending with -1, that marks physical channels
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* that are for different reasons not available for the driver.
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* @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
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@ -160,8 +158,6 @@ struct stedma40_platform_data {
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u32 dev_len;
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const dma_addr_t *dev_tx;
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const dma_addr_t *dev_rx;
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struct stedma40_chan_cfg *memcpy_conf_phy;
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struct stedma40_chan_cfg *memcpy_conf_log;
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int disabled_channels[STEDMA40_MAX_PHYS];
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int *soft_lli_chans;
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int num_of_soft_lli_chans;
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