mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 00:10:09 +00:00
iommu/arm-smmu: fix some checkpatch issues
Fix some issues reported by checkpatch.pl. Mostly whitespace, but also
includes min=>min_t, kzalloc=>kcalloc, and kmalloc=>kmalloc_array.
The only issue I'm leaving alone is:
arm-smmu.c:853: WARNING: line over 80 characters
#853: FILE: arm-smmu.c:853:
+ (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
since it seems to be a case where "exceeding 80 columns significantly
increases readability and does not hide information."
(Documentation/CodingStyle).
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Mitchel Humpherys
Will Deacon
parent
d3bca16635
commit
2907320df3
1 changed files with 37 additions and 22 deletions
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@ -317,9 +317,9 @@
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#define FSR_AFF (1 << 2)
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#define FSR_TF (1 << 1)
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#define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \
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FSR_TLBLKF)
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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#define FSR_IGN (FSR_AFF | FSR_ASF | \
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FSR_TLBMCF | FSR_TLBLKF)
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define FSYNR0_WNR (1 << 4)
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@ -405,7 +405,7 @@ struct arm_smmu_option_prop {
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const char *prop;
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};
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static struct arm_smmu_option_prop arm_smmu_options [] = {
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static struct arm_smmu_option_prop arm_smmu_options[] = {
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{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
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{ 0, NULL},
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};
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@ -413,6 +413,7 @@ static struct arm_smmu_option_prop arm_smmu_options [] = {
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static void parse_driver_options(struct arm_smmu_device *smmu)
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{
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int i = 0;
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do {
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if (of_property_read_bool(smmu->dev->of_node,
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arm_smmu_options[i].prop)) {
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@ -427,6 +428,7 @@ static struct device *dev_get_master_dev(struct device *dev)
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{
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if (dev_is_pci(dev)) {
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struct pci_bus *bus = to_pci_dev(dev)->bus;
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while (!pci_is_root_bus(bus))
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bus = bus->parent;
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return bus->bridge->parent;
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@ -442,6 +444,7 @@ static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
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while (node) {
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struct arm_smmu_master *master;
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master = container_of(node, struct arm_smmu_master, node);
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if (dev_node < master->of_node)
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@ -475,8 +478,8 @@ static int insert_smmu_master(struct arm_smmu_device *smmu,
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new = &smmu->masters.rb_node;
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parent = NULL;
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while (*new) {
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struct arm_smmu_master *this;
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this = container_of(*new, struct arm_smmu_master, node);
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struct arm_smmu_master *this
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= container_of(*new, struct arm_smmu_master, node);
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parent = *new;
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if (master->of_node < this->of_node)
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@ -716,7 +719,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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/* CBAR */
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reg = cfg->cbar;
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if (smmu->version == 1)
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reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
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reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
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/*
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* Use the weakest shareability/memory types, so they are
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@ -954,7 +957,7 @@ static int arm_smmu_domain_init(struct iommu_domain *domain)
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if (!smmu_domain)
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return -ENOMEM;
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pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
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pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
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if (!pgd)
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goto out_free_domain;
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smmu_domain->cfg.pgd = pgd;
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@ -971,6 +974,7 @@ static int arm_smmu_domain_init(struct iommu_domain *domain)
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static void arm_smmu_free_ptes(pmd_t *pmd)
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{
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pgtable_t table = pmd_pgtable(*pmd);
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pgtable_page_dtor(table);
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__free_page(table);
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}
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@ -1057,7 +1061,7 @@ static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
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if (cfg->smrs)
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return -EEXIST;
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smrs = kmalloc(sizeof(*smrs) * cfg->num_streamids, GFP_KERNEL);
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smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
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if (!smrs) {
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dev_err(smmu->dev, "failed to allocate %d SMRs\n",
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cfg->num_streamids);
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@ -1107,6 +1111,7 @@ static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
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/* Invalidate the SMRs before freeing back to the allocator */
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for (i = 0; i < cfg->num_streamids; ++i) {
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u8 idx = smrs[i].idx;
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writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
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__arm_smmu_free_bitmap(smmu->smr_map, idx);
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}
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@ -1123,6 +1128,7 @@ static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
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for (i = 0; i < cfg->num_streamids; ++i) {
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u16 sid = cfg->streamids[i];
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writel_relaxed(S2CR_TYPE_BYPASS,
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gr0_base + ARM_SMMU_GR0_S2CR(sid));
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}
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@ -1141,6 +1147,7 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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for (i = 0; i < cfg->num_streamids; ++i) {
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u32 idx, s2cr;
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idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
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s2cr = S2CR_TYPE_TRANS |
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(smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
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@ -1235,6 +1242,7 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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if (pmd_none(*pmd)) {
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/* Allocate a new set of tables */
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pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
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if (!table)
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return -ENOMEM;
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@ -1300,6 +1308,7 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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*/
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do {
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int i = 1;
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pteval &= ~ARM_SMMU_PTE_CONT;
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if (arm_smmu_pte_is_contiguous_range(addr, end)) {
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@ -1314,7 +1323,8 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
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cont_start = pmd_page_vaddr(*pmd) + idx;
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for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
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pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
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pte_val(*(cont_start + j)) &=
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~ARM_SMMU_PTE_CONT;
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arm_smmu_flush_pgtable(smmu, cont_start,
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sizeof(*pte) *
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@ -1617,7 +1627,8 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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/* Mark all SMRn as invalid and all S2CRn as bypass */
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
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writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
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writel_relaxed(S2CR_TYPE_BYPASS,
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gr0_base + ARM_SMMU_GR0_S2CR(i));
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}
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/* Make sure all context banks are disabled and clear CB_FSR */
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@ -1757,11 +1768,13 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
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/* Check for size mismatch of SMMU address space from mapped region */
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size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
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size = 1 <<
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(((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
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size *= (smmu->pagesize << 1);
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if (smmu->size != size)
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dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs "
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"from mapped region size (0x%lx)!\n", size, smmu->size);
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dev_warn(smmu->dev,
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"SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
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size, smmu->size);
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smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
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ID1_NUMS2CB_MASK;
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@ -1782,14 +1795,14 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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* allocation (PTRS_PER_PGD).
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*/
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#ifdef CONFIG_64BIT
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smmu->s1_output_size = min((unsigned long)VA_BITS, size);
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smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
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#else
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smmu->s1_output_size = min(32UL, size);
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#endif
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/* The stage-2 output mask is also applied for bypass */
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size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
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smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
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smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
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if (smmu->version == 1) {
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smmu->input_size = 32;
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@ -1813,7 +1826,8 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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dev_notice(smmu->dev,
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"\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
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smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
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smmu->input_size, smmu->s1_output_size,
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smmu->s2_output_size);
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return 0;
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}
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@ -1867,6 +1881,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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for (i = 0; i < num_irqs; ++i) {
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int irq = platform_get_irq(pdev, i);
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if (irq < 0) {
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dev_err(dev, "failed to get irq index %d\n", i);
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return -ENODEV;
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@ -1932,8 +1947,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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out_put_masters:
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for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
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struct arm_smmu_master *master;
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master = container_of(node, struct arm_smmu_master, node);
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struct arm_smmu_master *master
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= container_of(node, struct arm_smmu_master, node);
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of_node_put(master->of_node);
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}
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@ -1961,8 +1976,8 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
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return -ENODEV;
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for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
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struct arm_smmu_master *master;
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master = container_of(node, struct arm_smmu_master, node);
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struct arm_smmu_master *master
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= container_of(node, struct arm_smmu_master, node);
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of_node_put(master->of_node);
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}
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@ -1973,7 +1988,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
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free_irq(smmu->irqs[i], smmu);
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/* Turn the thing off */
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writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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return 0;
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}
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