ARM: dts: add DT for lan966 SoC and 2-port board pcb8291
This patch adds basic DT for Microchip lan966x SoC and associated board pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs. Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG and MCAN0. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220221080858.14233-1-kavyasree.kotagiri@microchip.com
This commit is contained in:
Kavyasree Kotagiri
Nicolas Ferre
parent
e783362eb5
commit
290deaa10c
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@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
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dtb-$(CONFIG_SOC_IMX7ULP) += \
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imx7ulp-com.dtb \
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imx7ulp-evk.dtb
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dtb-$(CONFIG_SOC_LAN966) += \
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lan966x-pcb8291.dtb
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dtb-$(CONFIG_SOC_LS1021A) += \
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ls1021a-moxa-uc-8410a.dtb \
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ls1021a-qds.dtb \
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@ -0,0 +1,64 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* lan966x_pcb8291.dts - Device Tree file for PCB8291
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*/
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/dts-v1/;
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#include "lan966x.dtsi"
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/ {
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model = "Microchip EVB - LAN9662";
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compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &usart3;
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};
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};
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&gpio {
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fc_shrd7_pins: fc_shrd7-pins {
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pins = "GPIO_49";
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function = "fc_shrd7";
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};
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fc_shrd8_pins: fc_shrd8-pins {
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pins = "GPIO_54";
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function = "fc_shrd8";
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};
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fc3_b_pins: fcb3-spi-pins {
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/* SCK, RXD, TXD */
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pins = "GPIO_51", "GPIO_52", "GPIO_53";
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function = "fc3_b";
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};
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can0_b_pins: can0_b_pins {
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/* RX, TX */
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pins = "GPIO_35", "GPIO_36";
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function = "can0_b";
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};
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};
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&can0 {
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pinctrl-0 = <&can0_b_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&flx3 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
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status = "okay";
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usart3: serial@200 {
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pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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};
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&watchdog {
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status = "okay";
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};
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@ -0,0 +1,237 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
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*
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* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
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*
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* Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mfd/atmel-flexcom.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/microchip,lan966x.h>
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/ {
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model = "Microchip LAN966 family SoC";
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compatible = "microchip,lan966";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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clock-frequency = <600000000>;
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reg = <0x0>;
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};
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};
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clocks {
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sys_clk: sys_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <162500000>;
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};
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cpu_clk: cpu_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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};
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ddr_clk: ddr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <300000000>;
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};
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nic_clk: nic_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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clks: clock-controller@e00c00a8 {
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compatible = "microchip,lan966x-gck";
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#clock-cells = <1>;
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clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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clock-names = "cpu", "ddr", "sys";
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reg = <0xe00c00a8 0x38>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <37500000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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flx0: flexcom@e0040000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0040000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0040000 0x800>;
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status = "disabled";
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};
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flx1: flexcom@e0044000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0044000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0044000 0x800>;
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status = "disabled";
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};
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trng: rng@e0048000 {
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compatible = "atmel,at91sam9g45-trng";
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reg = <0xe0048000 0x100>;
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clocks = <&nic_clk>;
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};
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aes: crypto@e004c000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xe004c000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
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<&dma0 AT91_XDMAC_DT_PERID(12)>;
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dma-names = "rx", "tx";
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clocks = <&nic_clk>;
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clock-names = "aes_clk";
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};
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flx2: flexcom@e0060000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0060000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0060000 0x800>;
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status = "disabled";
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};
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flx3: flexcom@e0064000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0064000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0064000 0x800>;
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status = "disabled";
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usart3: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&nic_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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};
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dma0: dma-controller@e0068000 {
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compatible = "microchip,sama7g5-dma";
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reg = <0xe0068000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&nic_clk>;
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clock-names = "dma_clk";
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};
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sha: crypto@e006c000 {
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compatible = "atmel,at91sam9g46-sha";
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reg = <0xe006c000 0xec>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
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dma-names = "tx";
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clocks = <&nic_clk>;
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clock-names = "sha_clk";
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};
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flx4: flexcom@e0070000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0070000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0070000 0x800>;
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status = "disabled";
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};
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timer0: timer@e008c000 {
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compatible = "snps,dw-apb-timer";
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reg = <0xe008c000 0x400>;
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clocks = <&nic_clk>;
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clock-names = "timer";
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog: watchdog@e0090000 {
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compatible = "snps,dw-wdt";
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reg = <0xe0090000 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&nic_clk>;
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status = "disabled";
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};
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can0: can@e081c000 {
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compatible = "bosch,m_can";
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reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&clks GCK_ID_MCAN0>;
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assigned-clock-rates = <40000000>;
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bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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gpio: pinctrl@e2004064 {
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compatible = "microchip,lan966x-pinctrl";
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reg = <0xe2004064 0xb4>,
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<0xe2010024 0x138>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 78>;
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interrupt-controller;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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};
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gic: interrupt-controller@e8c11000 {
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compatible = "arm,gic-400", "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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reg = <0xe8c11000 0x1000>,
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<0xe8c12000 0x2000>,
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<0xe8c14000 0x2000>,
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<0xe8c16000 0x2000>;
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};
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};
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};
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