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RDMA/hns: Adjust fields and variables about CMDQ tail/head

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The register 0x07014 is actually the head pointer of CMDQ, and 0x07010
means tail pointer. Current definitions are confusing, so rename them and
related variables.

The next_to_use of structure hns_roce_v2_cmq_ring has the same semantics
as head, merge them into one member. The next_to_clean of structure
hns_roce_v2_cmq_ring has the same semantics as tail. After deleting
next_to_clean, tail should also be deleted.

Link: https://lore.kernel.org/r/1612688143-28226-5-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Lang Cheng 2021-02-07 16:55:42 +08:00 committed by Jason Gunthorpe
parent 563aeb2266
commit 292b3352bd
3 changed files with 21 additions and 23 deletions
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4
drivers/infiniband/hw/hns/hns_roce_common.h
View file

@ -364,8 +364,8 @@
#define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000
#define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004
#define ROCEE_TX_CMQ_DEPTH_REG 0x07008
#define ROCEE_TX_CMQ_TAIL_REG 0x07010
#define ROCEE_TX_CMQ_HEAD_REG 0x07014
#define ROCEE_TX_CMQ_HEAD_REG 0x07010
#define ROCEE_TX_CMQ_TAIL_REG 0x07014
#define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018
#define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c

37
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
View file

@ -1169,7 +1169,7 @@ static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
&priv->cmq.csq : &priv->cmq.crq;
ring->flag = ring_type;
ring->next_to_use = 0;
ring->head = 0;
return hns_roce_alloc_cmq_desc(hr_dev, ring);
}
@ -1268,10 +1268,10 @@ static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
{
u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_TAIL_REG);
struct hns_roce_v2_priv *priv = hr_dev->priv;
return head == priv->cmq.csq.next_to_use;
return tail == priv->cmq.csq.head;
}
static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
@ -1283,25 +1283,25 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
u32 timeout = 0;
int handle = 0;
u16 desc_ret;
u32 tail;
int ret;
int ntc;
spin_lock_bh(&csq->lock);
ntc = csq->next_to_use;
tail = csq->head;
while (handle < num) {
desc_to_use = &csq->desc[csq->next_to_use];
desc_to_use = &csq->desc[csq->head];
*desc_to_use = desc[handle];
dev_dbg(hr_dev->dev, "set cmq desc:\n");
csq->next_to_use++;
if (csq->next_to_use == csq->desc_num)
csq->next_to_use = 0;
csq->head++;
if (csq->head == csq->desc_num)
csq->head = 0;
handle++;
}
/* Write to hardware */
roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, csq->head);
/*
* If the command is sync, wait for the firmware to write back,
@ -1321,24 +1321,25 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
ret = 0;
while (handle < num) {
/* get the result of hardware write back */
desc_to_use = &csq->desc[ntc];
desc_to_use = &csq->desc[tail];
desc[handle] = *desc_to_use;
dev_dbg(hr_dev->dev, "Get cmq desc:\n");
desc_ret = le16_to_cpu(desc[handle].retval);
if (unlikely(desc_ret != CMD_EXEC_SUCCESS))
ret = -EIO;
ntc++;
tail++;
handle++;
if (ntc == csq->desc_num)
ntc = 0;
if (tail == csq->desc_num)
tail = 0;
}
} else {
/* FW/HW reset or incorrect number of desc */
ntc = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
dev_warn(hr_dev->dev, "CMDQ move head from %d to %d\n",
csq->next_to_use, ntc);
csq->next_to_use = ntc;
tail = roce_read(hr_dev, ROCEE_TX_CMQ_TAIL_REG);
dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n",
csq->head, tail);
csq->head = tail;
ret = -EAGAIN;
}

3
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
View file

@ -1876,11 +1876,8 @@ struct hns_roce_v2_cmq_ring {
dma_addr_t desc_dma_addr;
struct hns_roce_cmq_desc *desc;
u32 head;
u32 tail;
u16 buf_size;
u16 desc_num;
int next_to_use;
u8 flag;
spinlock_t lock; /* command queue lock */
};