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scsi: pm80xx: Mask and unmask upper interrupt vectors 32-63
When upper inbound and outbound queues 32-63 are enabled, we see upper
vectors 32-63 in interrupt service routine. We need corresponding registers
to handle masking and unmasking of these upper interrupts.
To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and
MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit 0-31
represents interrupt vectors 32-63.
Link: https://lore.kernel.org/r/20220411064603.668448-2-Ajish.Koshy@microchip.com
Fixes: 05c6c029a4
("scsi: pm80xx: Increase number of supported queues")
Reviewed-by: John Garry <john.garry@huawei.com>
Acked-by: Jack Wang <jinpu.wang@ionos.com>
Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
Signed-off-by: Viswas G <Viswas.G@microchip.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
parent
f19fe8f354
commit
294080eacf
1 changed files with 13 additions and 9 deletions
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@ -1727,10 +1727,11 @@ static void
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pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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{
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#ifdef PM8001_USE_MSIX
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u32 mask;
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mask = (u32)(1 << vec);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
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if (vec < 32)
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
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else
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
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1U << (vec - 32));
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return;
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#endif
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pm80xx_chip_intx_interrupt_enable(pm8001_ha);
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@ -1746,12 +1747,15 @@ static void
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pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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{
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#ifdef PM8001_USE_MSIX
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u32 mask;
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if (vec == 0xFF)
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mask = 0xFFFFFFFF;
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if (vec == 0xFF) {
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/* disable all vectors 0-31, 32-63 */
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
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} else if (vec < 32)
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
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else
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mask = (u32)(1 << vec);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
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1U << (vec - 32));
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return;
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#endif
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pm80xx_chip_intx_interrupt_disable(pm8001_ha);
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