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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/amd/pp: delete dead code of arbiter overdriver clk
for sclk/mclk, can be adjusted through sysfs. for uvd/vce clk, will be adjusted case by case when requested. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
2456252368
commit
29411f05c6
10 changed files with 10 additions and 187 deletions
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@ -728,9 +728,6 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
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if (clock < stable_pstate_sclk)
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if (clock < stable_pstate_sclk)
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clock = stable_pstate_sclk;
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clock = stable_pstate_sclk;
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} else {
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if (clock < hwmgr->gfx_arbiter.sclk)
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clock = hwmgr->gfx_arbiter.sclk;
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}
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}
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if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
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if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
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@ -1085,14 +1082,8 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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uint32_t num_of_active_displays = 0;
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uint32_t num_of_active_displays = 0;
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struct cgs_display_info info = {0};
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struct cgs_display_info info = {0};
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cz_ps->evclk = hwmgr->vce_arbiter.evclk;
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cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
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cz_ps->need_dfs_bypass = true;
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cz_ps->need_dfs_bypass = true;
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cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
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hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
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cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
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cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
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clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
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clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
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@ -1105,9 +1096,6 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
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clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
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clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
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if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
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clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
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force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
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force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
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|| (num_of_active_displays >= 3);
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|| (num_of_active_displays >= 3);
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@ -1339,22 +1327,13 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
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cz_hwmgr->vce_dpm.hard_min_clk,
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cz_hwmgr->vce_dpm.hard_min_clk,
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PPSMC_MSG_SetEclkHardMin));
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PPSMC_MSG_SetEclkHardMin));
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} else {
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} else {
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/*Program HardMin based on the vce_arbiter.ecclk */
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if (hwmgr->vce_arbiter.ecclk == 0) {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetEclkHardMin, 0);
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PPSMC_MSG_SetEclkHardMin, 0);
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/* disable ECLK DPM 0. Otherwise VCE could hang if
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/* disable ECLK DPM 0. Otherwise VCE could hang if
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* switching SCLK from DPM 0 to 6/7 */
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* switching SCLK from DPM 0 to 6/7 */
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetEclkSoftMin, 1);
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PPSMC_MSG_SetEclkSoftMin, 1);
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} else {
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cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetEclkHardMin,
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cz_get_eclk_level(hwmgr,
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cz_hwmgr->vce_dpm.hard_min_clk,
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PPSMC_MSG_SetEclkHardMin));
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}
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}
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}
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return 0;
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return 0;
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}
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}
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@ -159,7 +159,6 @@ static int rv_construct_boot_state(struct pp_hwmgr *hwmgr)
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static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
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static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
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{
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{
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struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
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struct PP_Clocks clocks = {0};
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struct PP_Clocks clocks = {0};
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struct pp_display_clock_request clock_req;
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struct pp_display_clock_request clock_req;
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@ -170,39 +169,6 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
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PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
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PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
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"Attempt to set DCF Clock Failed!", return -EINVAL);
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"Attempt to set DCF Clock Failed!", return -EINVAL);
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if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) ||
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((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
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rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
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rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMinVcn,
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(rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
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}
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if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
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((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinSocclkByFreq,
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hwmgr->gfx_arbiter.sclk_hard_min / 100);
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rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);
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}
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if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
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(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetMinVideoGfxclkFreq,
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hwmgr->gfx_arbiter.gfxclk / 100);
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rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);
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}
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if ((hwmgr->gfx_arbiter.fclk != 0) &&
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(rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetMinVideoFclkFreq,
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hwmgr->gfx_arbiter.fclk / 100);
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rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);
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}
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return 0;
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return 0;
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}
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}
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@ -2722,9 +2722,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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}
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}
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}
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}
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smu7_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
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smu7_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
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cgs_get_active_displays_info(hwmgr->device, &info);
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cgs_get_active_displays_info(hwmgr->device, &info);
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minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
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minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
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@ -2754,38 +2751,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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minimum_clocks.memoryClock = stable_pstate_mclk;
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minimum_clocks.memoryClock = stable_pstate_mclk;
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}
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}
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if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
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minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
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if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
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minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
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smu7_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
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if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
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PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
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hwmgr->platform_descriptor.overdriveLimit.engineClock),
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"Overdrive sclk exceeds limit",
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hwmgr->gfx_arbiter.sclk_over_drive =
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hwmgr->platform_descriptor.overdriveLimit.engineClock);
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if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
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smu7_ps->performance_levels[1].engine_clock =
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hwmgr->gfx_arbiter.sclk_over_drive;
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}
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if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
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PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
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hwmgr->platform_descriptor.overdriveLimit.memoryClock),
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"Overdrive mclk exceeds limit",
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hwmgr->gfx_arbiter.mclk_over_drive =
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hwmgr->platform_descriptor.overdriveLimit.memoryClock);
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if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
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smu7_ps->performance_levels[1].memory_clock =
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hwmgr->gfx_arbiter.mclk_over_drive;
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}
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disable_mclk_switching_for_frame_lock = phm_cap_enabled(
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disable_mclk_switching_for_frame_lock = phm_cap_enabled(
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hwmgr->platform_descriptor.platformCaps,
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hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
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PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
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@ -3124,9 +3124,6 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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}
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}
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}
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}
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vega10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
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vega10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
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cgs_get_active_displays_info(hwmgr->device, &info);
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cgs_get_active_displays_info(hwmgr->device, &info);
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/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
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/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
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@ -3165,38 +3162,6 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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minimum_clocks.memoryClock = stable_pstate_mclk;
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minimum_clocks.memoryClock = stable_pstate_mclk;
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}
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}
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if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
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minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
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if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
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minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
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vega10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
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if (hwmgr->gfx_arbiter.sclk_over_drive) {
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PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
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hwmgr->platform_descriptor.overdriveLimit.engineClock),
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"Overdrive sclk exceeds limit",
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hwmgr->gfx_arbiter.sclk_over_drive =
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hwmgr->platform_descriptor.overdriveLimit.engineClock);
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if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
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vega10_ps->performance_levels[1].gfx_clock =
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hwmgr->gfx_arbiter.sclk_over_drive;
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}
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if (hwmgr->gfx_arbiter.mclk_over_drive) {
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PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
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hwmgr->platform_descriptor.overdriveLimit.memoryClock),
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"Overdrive mclk exceeds limit",
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hwmgr->gfx_arbiter.mclk_over_drive =
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hwmgr->platform_descriptor.overdriveLimit.memoryClock);
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if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
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vega10_ps->performance_levels[1].mem_clock =
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hwmgr->gfx_arbiter.mclk_over_drive;
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}
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disable_mclk_switching_for_frame_lock = phm_cap_enabled(
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disable_mclk_switching_for_frame_lock = phm_cap_enabled(
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hwmgr->platform_descriptor.platformCaps,
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hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
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PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
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@ -3819,10 +3784,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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uint32_t low_sclk_interrupt_threshold = 0;
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uint32_t low_sclk_interrupt_threshold = 0;
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if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
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if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
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(hwmgr->gfx_arbiter.sclk_threshold !=
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(data->low_sclk_interrupt_threshold != 0)) {
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data->low_sclk_interrupt_threshold)) {
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data->low_sclk_interrupt_threshold =
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hwmgr->gfx_arbiter.sclk_threshold;
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low_sclk_interrupt_threshold =
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low_sclk_interrupt_threshold =
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data->low_sclk_interrupt_threshold;
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data->low_sclk_interrupt_threshold;
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@ -105,36 +105,6 @@ struct phm_set_power_state_input {
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const struct pp_hw_power_state *pnew_state;
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const struct pp_hw_power_state *pnew_state;
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};
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};
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struct phm_acp_arbiter {
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uint32_t acpclk;
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};
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struct phm_uvd_arbiter {
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uint32_t vclk;
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uint32_t dclk;
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uint32_t vclk_ceiling;
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uint32_t dclk_ceiling;
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uint32_t vclk_soft_min;
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uint32_t dclk_soft_min;
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};
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struct phm_vce_arbiter {
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uint32_t evclk;
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uint32_t ecclk;
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};
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struct phm_gfx_arbiter {
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uint32_t sclk;
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uint32_t sclk_hard_min;
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uint32_t mclk;
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uint32_t sclk_over_drive;
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uint32_t mclk_over_drive;
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uint32_t sclk_threshold;
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uint32_t num_cus;
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uint32_t gfxclk;
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uint32_t fclk;
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};
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struct phm_clock_array {
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struct phm_clock_array {
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uint32_t count;
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uint32_t count;
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uint32_t values[1];
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uint32_t values[1];
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@ -737,10 +707,6 @@ struct pp_hwmgr {
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enum amd_dpm_forced_level dpm_level;
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enum amd_dpm_forced_level dpm_level;
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enum amd_dpm_forced_level saved_dpm_level;
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enum amd_dpm_forced_level saved_dpm_level;
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enum amd_dpm_forced_level request_dpm_level;
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enum amd_dpm_forced_level request_dpm_level;
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struct phm_gfx_arbiter gfx_arbiter;
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struct phm_acp_arbiter acp_arbiter;
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struct phm_uvd_arbiter uvd_arbiter;
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struct phm_vce_arbiter vce_arbiter;
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uint32_t usec_timeout;
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uint32_t usec_timeout;
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void *pptable;
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void *pptable;
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struct phm_platform_descriptor platform_descriptor;
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struct phm_platform_descriptor platform_descriptor;
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@ -2218,10 +2218,7 @@ static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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||||||
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||||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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||||||
PHM_PlatformCaps_SclkThrottleLowNotification)
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PHM_PlatformCaps_SclkThrottleLowNotification)
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||||||
&& (hwmgr->gfx_arbiter.sclk_threshold !=
|
&& (data->low_sclk_interrupt_threshold != 0)) {
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||||||
data->low_sclk_interrupt_threshold)) {
|
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||||||
data->low_sclk_interrupt_threshold =
|
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||||||
hwmgr->gfx_arbiter.sclk_threshold;
|
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||||||
low_sclk_interrupt_threshold =
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low_sclk_interrupt_threshold =
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||||||
data->low_sclk_interrupt_threshold;
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data->low_sclk_interrupt_threshold;
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||||||
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||||||
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@ -2385,10 +2385,7 @@ static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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||||||
|
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||||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
PHM_PlatformCaps_SclkThrottleLowNotification)
|
PHM_PlatformCaps_SclkThrottleLowNotification)
|
||||||
&& (hwmgr->gfx_arbiter.sclk_threshold !=
|
&& (data->low_sclk_interrupt_threshold != 0)) {
|
||||||
data->low_sclk_interrupt_threshold)) {
|
|
||||||
data->low_sclk_interrupt_threshold =
|
|
||||||
hwmgr->gfx_arbiter.sclk_threshold;
|
|
||||||
low_sclk_interrupt_threshold =
|
low_sclk_interrupt_threshold =
|
||||||
data->low_sclk_interrupt_threshold;
|
data->low_sclk_interrupt_threshold;
|
||||||
|
|
||||||
|
|
|
@ -2202,10 +2202,7 @@ static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
|
||||||
|
|
||||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
PHM_PlatformCaps_SclkThrottleLowNotification)
|
PHM_PlatformCaps_SclkThrottleLowNotification)
|
||||||
&& (hwmgr->gfx_arbiter.sclk_threshold !=
|
&& (data->low_sclk_interrupt_threshold != 0)) {
|
||||||
data->low_sclk_interrupt_threshold)) {
|
|
||||||
data->low_sclk_interrupt_threshold =
|
|
||||||
hwmgr->gfx_arbiter.sclk_threshold;
|
|
||||||
low_sclk_interrupt_threshold =
|
low_sclk_interrupt_threshold =
|
||||||
data->low_sclk_interrupt_threshold;
|
data->low_sclk_interrupt_threshold;
|
||||||
|
|
||||||
|
|
|
@ -2369,10 +2369,7 @@ static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
|
||||||
|
|
||||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
PHM_PlatformCaps_SclkThrottleLowNotification)
|
PHM_PlatformCaps_SclkThrottleLowNotification)
|
||||||
&& (hwmgr->gfx_arbiter.sclk_threshold !=
|
&& (data->low_sclk_interrupt_threshold != 0)) {
|
||||||
data->low_sclk_interrupt_threshold)) {
|
|
||||||
data->low_sclk_interrupt_threshold =
|
|
||||||
hwmgr->gfx_arbiter.sclk_threshold;
|
|
||||||
low_sclk_interrupt_threshold =
|
low_sclk_interrupt_threshold =
|
||||||
data->low_sclk_interrupt_threshold;
|
data->low_sclk_interrupt_threshold;
|
||||||
|
|
||||||
|
|
|
@ -2654,10 +2654,7 @@ static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
|
||||||
|
|
||||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
PHM_PlatformCaps_SclkThrottleLowNotification)
|
PHM_PlatformCaps_SclkThrottleLowNotification)
|
||||||
&& (hwmgr->gfx_arbiter.sclk_threshold !=
|
&& (data->low_sclk_interrupt_threshold != 0)) {
|
||||||
data->low_sclk_interrupt_threshold)) {
|
|
||||||
data->low_sclk_interrupt_threshold =
|
|
||||||
hwmgr->gfx_arbiter.sclk_threshold;
|
|
||||||
low_sclk_interrupt_threshold =
|
low_sclk_interrupt_threshold =
|
||||||
data->low_sclk_interrupt_threshold;
|
data->low_sclk_interrupt_threshold;
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue