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PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0

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Add missing bits from PCIe 4.0 and updates for PCIe 5.0 r1.0.

PCIe 4.0:
Device Status bit 6 - W1C - Emergency Power Reduction Detected
Link Control bits 15:14 - RW - DRS Signaling Control
Slot Control bit 13 - RW - Auto Slow Power Limit Disable

PCIe 5.0:
Slot Control bit 14 - RW - In-Band PD Disable

Link: https://lore.kernel.org/r/20200511162117.6674-4-jonathan.derrick@intel.com
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Jon Derrick 2020-05-11 12:21:16 -04:00 committed by Lorenzo Pieralisi
parent f61959b6e2
commit 2960865127
1 changed files with 16 additions and 15 deletions
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31
drivers/pci/pci-bridge-emul.c
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@ -181,12 +181,12 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
.rw = GENMASK(15, 0),
/*
* Device status register has 4 bits W1C, then 2 bits
* RO, the rest is reserved
* Device status register has bits 6 and [3:0] W1C, [5:4] RO,
* the rest is reserved
*/
.w1c = GENMASK(19, 16),
.ro = GENMASK(21, 20),
.rsvd = GENMASK(31, 22),
.w1c = (BIT(6) | GENMASK(3, 0)) << 16,
.ro = GENMASK(5, 4) << 16,
.rsvd = GENMASK(15, 7) << 16,
},
[PCI_EXP_LNKCAP / 4] = {
@ -197,15 +197,16 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
[PCI_EXP_LNKCTL / 4] = {
/*
* Link control has bits [1:0] and [11:3] RW, the
* other bits are reserved.
* Link status has bits [13:0] RO, and bits [14:15]
* Link control has bits [15:14], [11:3] and [1:0] RW, the
* rest is reserved.
*
* Link status has bits [13:0] RO, and bits [15:14]
* W1C.
*/
.rw = GENMASK(11, 3) | GENMASK(1, 0),
.rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0),
.ro = GENMASK(13, 0) << 16,
.w1c = GENMASK(15, 14) << 16,
.rsvd = GENMASK(15, 12) | BIT(2),
.rsvd = GENMASK(13, 12) | BIT(2),
},
[PCI_EXP_SLTCAP / 4] = {
@ -214,19 +215,19 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
[PCI_EXP_SLTCTL / 4] = {
/*
* Slot control has bits [12:0] RW, the rest is
* Slot control has bits [14:0] RW, the rest is
* reserved.
*
* Slot status has a mix of W1C and RO bits, as well
* as reserved bits.
* Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
* rest is reserved.
*/
.rw = GENMASK(12, 0),
.rw = GENMASK(14, 0),
.w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
.ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
PCI_EXP_SLTSTA_EIS) << 16,
.rsvd = GENMASK(15, 13) | (GENMASK(15, 9) << 16),
.rsvd = GENMASK(15) | (GENMASK(15, 9) << 16),
},
[PCI_EXP_RTCTL / 4] = {