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clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
All Exynos5250 boards have been fully converted to device-tree and use generic dt-based CPUfreq driver, so there is no need to create any clkdev aliases for the clocks. Drop all the code related to aliases handling. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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6de08891c8
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29964890f3
1 changed files with 9 additions and 9 deletions
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@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
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/*
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/*
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* CMU_CPU
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* CMU_CPU
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*/
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*/
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MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT, 0, "mout_apll"),
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CLK_SET_RATE_PARENT, 0),
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MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
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MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
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/*
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/*
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* CMU_CORE
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* CMU_CORE
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*/
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*/
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MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
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MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
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/*
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/*
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* CMU_TOP
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* CMU_TOP
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@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
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*/
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*/
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DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
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DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
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DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
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DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
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DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
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DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
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/*
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/*
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* CMU_TOP
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* CMU_TOP
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@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
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};
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};
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static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
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static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
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[apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
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APLL_LOCK, APLL_CON0, "fout_apll", NULL),
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APLL_CON0, NULL),
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[mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
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MPLL_CON0, NULL),
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[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
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[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
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BPLL_CON0, NULL),
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BPLL_CON0, NULL),
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[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
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[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
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