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ASoC: sgtl5000: Fix the cache handling
Since commit e5d80e82e3
(ASoC: sgtl5000: Convert to use regmap directly) a
kernel oops is observed after a suspend/resume sequence.
The kernel oops happens inside sgtl5000_restore_regs() as codec->reg_cache is no
longer a valid pointer.
Add the remaining register entries into sgtl5000_reg_defaults[] and remove
sgtl5000_restore_regs() completely, which allows suspend/resume to work fine and
make the code simpler.
Tested on a im53-qsb board.
Reported-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
parent
63e54cd9ca
commit
29aa37cddf
1 changed files with 15 additions and 60 deletions
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@ -36,18 +36,32 @@
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/* default value of sgtl5000 registers */
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static const struct reg_default sgtl5000_reg_defaults[] = {
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{ SGTL5000_CHIP_DIG_POWER, 0x0000 },
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{ SGTL5000_CHIP_CLK_CTRL, 0x0008 },
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{ SGTL5000_CHIP_I2S_CTRL, 0x0010 },
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{ SGTL5000_CHIP_SSS_CTRL, 0x0010 },
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{ SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
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{ SGTL5000_CHIP_DAC_VOL, 0x3c3c },
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{ SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
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{ SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
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{ SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
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{ SGTL5000_CHIP_ANA_CTRL, 0x0111 },
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{ SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
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{ SGTL5000_CHIP_REF_CTRL, 0x0000 },
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{ SGTL5000_CHIP_MIC_CTRL, 0x0000 },
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{ SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
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{ SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
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{ SGTL5000_CHIP_ANA_POWER, 0x7060 },
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{ SGTL5000_CHIP_PLL_CTRL, 0x5000 },
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{ SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
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{ SGTL5000_CHIP_ANA_STATUS, 0x0000 },
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{ SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
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{ SGTL5000_CHIP_ANA_TEST2, 0x0000 },
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{ SGTL5000_DAP_CTRL, 0x0000 },
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{ SGTL5000_DAP_PEQ, 0x0000 },
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{ SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
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{ SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
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{ SGTL5000_DAP_AUDIO_EQ, 0x0000 },
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{ SGTL5000_DAP_SURROUND, 0x0040 },
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{ SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
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{ SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
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@ -55,6 +69,7 @@ static const struct reg_default sgtl5000_reg_defaults[] = {
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{ SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
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{ SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
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{ SGTL5000_DAP_MAIN_CHAN, 0x8000 },
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{ SGTL5000_DAP_MIX_CHAN, 0x0000 },
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{ SGTL5000_DAP_AVC_CTRL, 0x0510 },
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{ SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
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{ SGTL5000_DAP_AVC_ATTACK, 0x0028 },
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@ -1068,71 +1083,11 @@ static int sgtl5000_suspend(struct snd_soc_codec *codec)
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return 0;
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}
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/*
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* restore all sgtl5000 registers,
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* since a big hole between dap and regular registers,
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* we will restore them respectively.
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*/
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static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
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{
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u16 *cache = codec->reg_cache;
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u16 reg;
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/* restore regular registers */
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for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
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/* These regs should restore in particular order */
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if (reg == SGTL5000_CHIP_ANA_POWER ||
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reg == SGTL5000_CHIP_CLK_CTRL ||
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reg == SGTL5000_CHIP_LINREG_CTRL ||
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reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
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reg == SGTL5000_CHIP_REF_CTRL)
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continue;
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snd_soc_write(codec, reg, cache[reg]);
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}
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/* restore dap registers */
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for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
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snd_soc_write(codec, reg, cache[reg]);
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/*
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* restore these regs according to the power setting sequence in
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* sgtl5000_set_power_regs() and clock setting sequence in
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* sgtl5000_set_clock().
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*
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* The order of restore is:
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* 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
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* SGTL5000_CHIP_ANA_POWER PLL bits set
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* 2. SGTL5000_CHIP_LINREG_CTRL should be set before
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* SGTL5000_CHIP_ANA_POWER LINREG_D restored
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* 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
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* prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
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*/
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snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
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cache[SGTL5000_CHIP_LINREG_CTRL]);
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snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
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cache[SGTL5000_CHIP_ANA_POWER]);
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snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
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cache[SGTL5000_CHIP_CLK_CTRL]);
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snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
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cache[SGTL5000_CHIP_REF_CTRL]);
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snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
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cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
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return 0;
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}
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static int sgtl5000_resume(struct snd_soc_codec *codec)
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{
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/* Bring the codec back up to standby to enable regulators */
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sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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/* Restore registers by cached in memory */
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sgtl5000_restore_regs(codec);
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return 0;
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}
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#else
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