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clk: ingenic: Use to_clk_info() macro for all clocks
The to_clk_info() previously had a BUG_ON() to check that it was only called for PLL clocks. Yet, all the other clocks were doing the exact same thing the macro does, in-line. Move the to_clk_info() macro to the top of the file, remove the hardcoded BUG_ON(), and use it everywhere it makes sense. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
9123e3a74e
commit
29c37341b5
1 changed files with 15 additions and 39 deletions
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@ -21,6 +21,12 @@
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#define MHZ (1000 * 1000)
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static inline const struct ingenic_cgu_clk_info *
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to_clk_info(struct ingenic_clk *clk)
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{
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return &clk->cgu->clock_info[clk->idx];
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}
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/**
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* ingenic_cgu_gate_get() - get the value of clock gate register bit
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* @cgu: reference to the CGU whose registers should be read
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@ -71,14 +77,13 @@ static unsigned long
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ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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const struct ingenic_cgu_pll_info *pll_info;
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unsigned m, n, od_enc, od;
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bool bypass;
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u32 ctl;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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BUG_ON(clk_info->type != CGU_CLK_PLL);
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pll_info = &clk_info->pll;
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@ -144,18 +149,6 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
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n * od);
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}
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static inline const struct ingenic_cgu_clk_info *to_clk_info(
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struct ingenic_clk *ingenic_clk)
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{
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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BUG_ON(clk_info->type != CGU_CLK_PLL);
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return clk_info;
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}
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static long
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ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *prate)
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@ -290,13 +283,11 @@ static const struct clk_ops ingenic_pll_ops = {
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static u8 ingenic_clk_get_parent(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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u32 reg;
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u8 i, hw_idx, idx = 0;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_MUX) {
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reg = readl(cgu->base + clk_info->mux.reg);
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hw_idx = (reg >> clk_info->mux.shift) &
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@ -318,14 +309,12 @@ static u8 ingenic_clk_get_parent(struct clk_hw *hw)
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static int ingenic_clk_set_parent(struct clk_hw *hw, u8 idx)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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unsigned long flags;
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u8 curr_idx, hw_idx, num_poss;
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u32 reg, mask;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_MUX) {
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/*
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* Convert the parent index to the hardware index by adding
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@ -368,13 +357,11 @@ static unsigned long
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ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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unsigned long rate = parent_rate;
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u32 div_reg, div;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_DIV) {
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div_reg = readl(cgu->base + clk_info->div.reg);
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div = (div_reg >> clk_info->div.shift) &
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@ -443,12 +430,9 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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unsigned int div = 1;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_DIV)
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div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
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else if (clk_info->type & CGU_CLK_FIXDIV)
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@ -462,16 +446,14 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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const unsigned timeout = 100;
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unsigned long rate, flags;
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unsigned int hw_div, div, i;
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u32 reg, mask;
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int ret = 0;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_DIV) {
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div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
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rate = DIV_ROUND_UP(parent_rate, div);
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@ -525,12 +507,10 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
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static int ingenic_clk_enable(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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unsigned long flags;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_GATE) {
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/* ungate the clock */
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spin_lock_irqsave(&cgu->lock, flags);
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@ -547,12 +527,10 @@ static int ingenic_clk_enable(struct clk_hw *hw)
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static void ingenic_clk_disable(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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unsigned long flags;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_GATE) {
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/* gate the clock */
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spin_lock_irqsave(&cgu->lock, flags);
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@ -564,12 +542,10 @@ static void ingenic_clk_disable(struct clk_hw *hw)
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static int ingenic_clk_is_enabled(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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int enabled = 1;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_GATE)
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enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
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