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perf tools fixes and improvements for v6.10: 

- Add Kan Liang to MAINTAINERS as a perf tools reviewer.
 
 - Add support for using the 'capstone' disassembler library in various tools,
   such as 'perf script' and 'perf annotate'. This is an alternative for the
   use of the 'xed' and 'objdump' disassemblers.
 
 - Data-type profiling improvements:
 
   Resolve types for a->b->c by backtracking the assignments until it finds
   DWARF info for one of those members
 
   Support for global variables, keeping a cache to speed up lookups.
 
   Handle the 'call' instruction, dealing with effects on registers and handling
   its return when tracking register data types.
 
   Handle x86's segment based addressing like %gs:0x28, to support things like
   per CPU variables, the stack canary, etc.
 
   Data-type profiling got big speedups when using capstone for disassembling.
   The objdump outoput parsing method is left as a fallback when capstone fails or
   isn't available. There are patches posted for 6.11 that to use a LLVM
   disassembler.
 
   Support event group display in the TUI when annotating types with --data-type,
   for instance to show memory load and store events for the data type fields.
 
   Optimize the 'perf annotate' data structures, reducing memory usage.
 
   Add a initial 'perf test' for 'perf annotate', checking that a target symbol
   appears on the output, specifying objdump via the command line, etc.
 
 - Integrate the shellcheck utility with the build of perf to allow catching
   shell problems early in areas such as 'perf test', 'perf trace' scrape
   scripts, etc.
 
 - Add 'uretprobe' variant in the 'perf bench uprobe' tool.
 
 - Add script to run instances of 'perf script' in parallel.
 
 - Allow parsing tracepoint names that start with digits, such as
   9p/9p_client_req, etc. Make sure 'perf test' tests it even on systems
   where those tracepoints aren't available.
 
 Vendor Events:
 
 - Update Intel JSON files for Cascade Lake X, Emerald Rapids, Grand Ridge, Ice
   Lake X, Lunar Lake, Meteor Lake, Sapphire Rapids, Sierra Forest, Sky Lake X,
   Sky Lake and Snow Ridge X.  Remove info metrics erroneously in TopdownL1.
 
 - Add AMD's Zen 5 core and uncore events and metrics. Those come from the
   "Performance Monitor Counters for AMD Family 1Ah Model 00h- 0Fh Processors"
   document, with events that capture information on op dispatch, execution and
   retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc.
 
 - Mark L1D_CACHE_INVAL impacted by errata for ARM64's AmpereOne/AmpereOneX.
 
 Miscellaneous:
 
 - Sync header copies with the kernel sources.
 
 - Move some header copies used only for generating translation string tables
   for ioctl cmds and other syscall integer arguments to a new directory under
   tools/perf/beauty/, to separate from copies in tools/include/ that are used
   to build the tools.
 
 - Introduce scrape script for several syscall 'flags'/'mask' arguments.
 
 - Improve cpumap utilization, fixing up pairing of refcounts, using the right
   iterators (perf_cpu_map__for_each_cpu), etc.
 
 - Give more details about raw event encodings in 'perf list', show tracepoint
   encoding in the detailed output.
 
 - Refactor the DSOs handling code, reducing memory usage.
 
 - Document the BPF event modifier and add a 'perf test' for it.
 
 - Improve the event parser, better error messages and add further 'perf test's
   for it.
 
 - Add reference count checking to 'struct comm_str' and 'struct mem_info'.
 
 - Make ARM64's 'perf test' entries for the Neoverse N1 more robust.
 
 - Tweak the ARM64's Coresight 'perf test's.
 
 - Improve ARM64's CoreSight ETM version detection and error reporting.
 
 - Fix handling of symbols when using kcore.
 
 - Fix PAI (Processor Activity Instrumentation) counter names for s390 virtual
   machines in 'perf report'.
 
 - Fix -g/--call-graph option failure in 'perf sched timehist'.
 
 - Add LIBTRACEEVENT_DIR build option to allow building with libtraceevent
   installed in non-standard directories, such as when doing cross builds.
 
 - Various 'perf test' and 'perf bench' fixes.
 
 - Improve 'perf probe' error message for long C++ probe names.
 
 Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Merge tag 'perf-tools-for-v6.10-1-2024-05-21' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools updates from Arnaldo Carvalho de Melo:
 "General:

   - Integrate the shellcheck utility with the build of perf to allow
     catching shell problems early in areas such as 'perf test', 'perf
     trace' scrape scripts, etc

   - Add 'uretprobe' variant in the 'perf bench uprobe' tool

   - Add script to run instances of 'perf script' in parallel

   - Allow parsing tracepoint names that start with digits, such as
     9p/9p_client_req, etc. Make sure 'perf test' tests it even on
     systems where those tracepoints aren't available

   - Add Kan Liang to MAINTAINERS as a perf tools reviewer

   - Add support for using the 'capstone' disassembler library in
     various tools, such as 'perf script' and 'perf annotate'. This is
     an alternative for the use of the 'xed' and 'objdump' disassemblers

  Data-type profiling improvements:

   - Resolve types for a->b->c by backtracking the assignments until it
     finds DWARF info for one of those members

   - Support for global variables, keeping a cache to speed up lookups

   - Handle the 'call' instruction, dealing with effects on registers
     and handling its return when tracking register data types

   - Handle x86's segment based addressing like %gs:0x28, to support
     things like per CPU variables, the stack canary, etc

   - Data-type profiling got big speedups when using capstone for
     disassembling. The objdump outoput parsing method is left as a
     fallback when capstone fails or isn't available. There are patches
     posted for 6.11 that to use a LLVM disassembler

   - Support event group display in the TUI when annotating types with
     --data-type, for instance to show memory load and store events for
     the data type fields

   - Optimize the 'perf annotate' data structures, reducing memory usage

   - Add a initial 'perf test' for 'perf annotate', checking that a
     target symbol appears on the output, specifying objdump via the
     command line, etc

  Vendor Events:

   - Update Intel JSON files for Cascade Lake X, Emerald Rapids, Grand
     Ridge, Ice Lake X, Lunar Lake, Meteor Lake, Sapphire Rapids, Sierra
     Forest, Sky Lake X, Sky Lake and Snow Ridge X. Remove info metrics
     erroneously in TopdownL1

   - Add AMD's Zen 5 core and uncore events and metrics. Those come from
     the "Performance Monitor Counters for AMD Family 1Ah Model 00h- 0Fh
     Processors" document, with events that capture information on op
     dispatch, execution and retirement, branch prediction, L1 and L2
     cache activity, TLB activity, etc

   - Mark L1D_CACHE_INVAL impacted by errata for ARM64's AmpereOne/
     AmpereOneX

  Miscellaneous:

   - Sync header copies with the kernel sources

   - Move some header copies used only for generating translation string
     tables for ioctl cmds and other syscall integer arguments to a new
     directory under tools/perf/beauty/, to separate from copies in
     tools/include/ that are used to build the tools

   - Introduce scrape script for several syscall 'flags'/'mask'
     arguments

   - Improve cpumap utilization, fixing up pairing of refcounts, using
     the right iterators (perf_cpu_map__for_each_cpu), etc

   - Give more details about raw event encodings in 'perf list', show
     tracepoint encoding in the detailed output

   - Refactor the DSOs handling code, reducing memory usage

   - Document the BPF event modifier and add a 'perf test' for it

   - Improve the event parser, better error messages and add further
     'perf test's for it

   - Add reference count checking to 'struct comm_str' and 'struct
     mem_info'

   - Make ARM64's 'perf test' entries for the Neoverse N1 more robust

   - Tweak the ARM64's Coresight 'perf test's

   - Improve ARM64's CoreSight ETM version detection and error reporting

   - Fix handling of symbols when using kcore

   - Fix PAI (Processor Activity Instrumentation) counter names for s390
     virtual machines in 'perf report'

   - Fix -g/--call-graph option failure in 'perf sched timehist'

   - Add LIBTRACEEVENT_DIR build option to allow building with
     libtraceevent installed in non-standard directories, such as when
     doing cross builds

   - Various 'perf test' and 'perf bench' fixes

   - Improve 'perf probe' error message for long C++ probe names"

* tag 'perf-tools-for-v6.10-1-2024-05-21' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (260 commits)
  tools lib subcmd: Show parent options in help
  perf pmu: Count sys and cpuid JSON events separately
  perf stat: Don't display metric header for non-leader uncore events
  perf annotate-data: Ensure the number of type histograms
  perf annotate: Fix segfault on sample histogram
  perf daemon: Fix file leak in daemon_session__control
  libsubcmd: Fix parse-options memory leak
  perf lock: Avoid memory leaks from strdup()
  perf sched: Rename 'switches' column header to 'count' and add usage description, options for latency
  perf tools: Ignore deleted cgroups
  perf parse: Allow tracepoint names to start with digits
  perf parse-events: Add new 'fake_tp' parameter for tests
  perf parse-events: pass parse_state to add_tracepoint
  perf symbols: Fix ownership of string in dso__load_vmlinux()
  perf symbols: Update kcore map before merging in remaining symbols
  perf maps: Re-use __maps__free_maps_by_name()
  perf symbols: Remove map from list before updating addresses
  perf tracepoint: Don't scan all tracepoints to test if one exists
  perf dwarf-aux: Fix build with HAVE_DWARF_CFI_SUPPORT
  perf thread: Fixes to thread__new() related to initializing comm
  ...
This commit is contained in:
Linus Torvalds 2024-05-21 15:45:14 -07:00
parent 4865a27c66 ea558c8624
commit 29c73fc794
304 changed files with 15205 additions and 6269 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/ABI/testing/sysfs-bus-event_source-devices-events
View File

@ -37,6 +37,12 @@ Description: Per-pmu performance monitoring events specific to the running syste
performance monitoring event supported by the <pmu>. The name
of the file is the name of the event.
As performance monitoring event names are case
insensitive in the perf tool, the perf tool only looks
for lower or upper case event names in sysfs to avoid
scanning the directory. It is therefore required the
name of the event here is either lower or upper case.
File contents:
<term>[=<value>][,<term>[=<value>]]...

1
MAINTAINERS
View File

@ -17541,6 +17541,7 @@ R: Alexander Shishkin <alexander.shishkin@linux.intel.com>
R: Jiri Olsa <jolsa@kernel.org>
R: Ian Rogers <irogers@google.com>
R: Adrian Hunter <adrian.hunter@intel.com>
R: "Liang, Kan" <kan.liang@linux.intel.com>
L: linux-perf-users@vger.kernel.org
L: linux-kernel@vger.kernel.org
S: Supported

7
tools/arch/x86/include/asm/cpufeatures.h
View File

@ -461,11 +461,15 @@
/*
* Extended auxiliary flags: Linux defined - for features scattered in various
* CPUID levels like 0x80000022, etc.
* CPUID levels like 0x80000022, etc and Linux defined features.
*
* Reuse free bits when adding new feature flags!
*/
#define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */
#define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */
#define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */
#define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */
#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */
/*
* BUG word(s)
@ -515,4 +519,5 @@
#define X86_BUG_SRSO X86_BUG(1*32 + 0) /* AMD SRSO bug */
#define X86_BUG_DIV0 X86_BUG(1*32 + 1) /* AMD DIV0 speculation bug */
#define X86_BUG_RFDS X86_BUG(1*32 + 2) /* CPU is vulnerable to Register File Data Sampling */
#define X86_BUG_BHI X86_BUG(1*32 + 3) /* CPU is affected by Branch History Injection */
#endif /* _ASM_X86_CPUFEATURES_H */

9
tools/arch/x86/include/asm/msr-index.h
View File

@ -61,10 +61,13 @@
#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
#define SPEC_CTRL_BHI_DIS_S_SHIFT 10 /* Disable Branch History Injection behavior */
#define SPEC_CTRL_BHI_DIS_S BIT(SPEC_CTRL_BHI_DIS_S_SHIFT)
/* A mask for bits which the kernel toggles when controlling mitigations */
#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
| SPEC_CTRL_RRSBA_DIS_S)
| SPEC_CTRL_RRSBA_DIS_S \
| SPEC_CTRL_BHI_DIS_S)
#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
@ -163,6 +166,10 @@
* are restricted to targets in
* kernel.
*/
#define ARCH_CAP_BHI_NO BIT(20) /*
* CPU is not affected by Branch
* History Injection.
*/
#define ARCH_CAP_PBRSB_NO BIT(24) /*
* Not susceptible to Post-Barrier
* Return Stack Buffer Predictions.

8
tools/include/linux/bits.h
View File

@ -4,6 +4,7 @@
#include <linux/const.h>
#include <vdso/bits.h>
#include <uapi/linux/bits.h>
#include <asm/bitsperlong.h>
#define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
@ -30,15 +31,8 @@
#define GENMASK_INPUT_CHECK(h, l) 0
#endif
#define __GENMASK(h, l) \
(((~UL(0)) - (UL(1) << (l)) + 1) & \
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
#define GENMASK(h, l) \
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
#define __GENMASK_ULL(h, l) \
(((~ULL(0)) - (ULL(1) << (l)) + 1) & \
(~ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h))))
#define GENMASK_ULL(h, l) \
(GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l))

4
tools/include/uapi/asm-generic/bitsperlong.h
View File

@ -24,4 +24,8 @@
#endif
#endif
#ifndef __BITS_PER_LONG_LONG
#define __BITS_PER_LONG_LONG 64
#endif
#endif /* _UAPI__ASM_GENERIC_BITS_PER_LONG */

221
tools/include/uapi/asm-generic/fcntl.h
View File

@ -1,221 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ASM_GENERIC_FCNTL_H
#define _ASM_GENERIC_FCNTL_H
#include <linux/types.h>
/*
* FMODE_EXEC is 0x20
* FMODE_NONOTIFY is 0x4000000
* These cannot be used by userspace O_* until internal and external open
* flags are split.
* -Eric Paris
*/
/*
* When introducing new O_* bits, please check its uniqueness in fcntl_init().
*/
#define O_ACCMODE 00000003
#define O_RDONLY 00000000
#define O_WRONLY 00000001
#define O_RDWR 00000002
#ifndef O_CREAT
#define O_CREAT 00000100 /* not fcntl */
#endif
#ifndef O_EXCL
#define O_EXCL 00000200 /* not fcntl */
#endif
#ifndef O_NOCTTY
#define O_NOCTTY 00000400 /* not fcntl */
#endif
#ifndef O_TRUNC
#define O_TRUNC 00001000 /* not fcntl */
#endif
#ifndef O_APPEND
#define O_APPEND 00002000
#endif
#ifndef O_NONBLOCK
#define O_NONBLOCK 00004000
#endif
#ifndef O_DSYNC
#define O_DSYNC 00010000 /* used to be O_SYNC, see below */
#endif
#ifndef FASYNC
#define FASYNC 00020000 /* fcntl, for BSD compatibility */
#endif
#ifndef O_DIRECT
#define O_DIRECT 00040000 /* direct disk access hint */
#endif
#ifndef O_LARGEFILE
#define O_LARGEFILE 00100000
#endif
#ifndef O_DIRECTORY
#define O_DIRECTORY 00200000 /* must be a directory */
#endif
#ifndef O_NOFOLLOW
#define O_NOFOLLOW 00400000 /* don't follow links */
#endif
#ifndef O_NOATIME
#define O_NOATIME 01000000
#endif
#ifndef O_CLOEXEC
#define O_CLOEXEC 02000000 /* set close_on_exec */
#endif
/*
* Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
* the O_SYNC flag. We continue to use the existing numerical value
* for O_DSYNC semantics now, but using the correct symbolic name for it.
* This new value is used to request true Posix O_SYNC semantics. It is
* defined in this strange way to make sure applications compiled against
* new headers get at least O_DSYNC semantics on older kernels.
*
* This has the nice side-effect that we can simply test for O_DSYNC
* wherever we do not care if O_DSYNC or O_SYNC is used.
*
* Note: __O_SYNC must never be used directly.
*/
#ifndef O_SYNC
#define __O_SYNC 04000000
#define O_SYNC (__O_SYNC|O_DSYNC)
#endif
#ifndef O_PATH
#define O_PATH 010000000
#endif
#ifndef __O_TMPFILE
#define __O_TMPFILE 020000000
#endif
/* a horrid kludge trying to make sure that this will fail on old kernels */
#define O_TMPFILE (__O_TMPFILE | O_DIRECTORY)
#ifndef O_NDELAY
#define O_NDELAY O_NONBLOCK
#endif
#define F_DUPFD 0 /* dup */
#define F_GETFD 1 /* get close_on_exec */
#define F_SETFD 2 /* set/clear close_on_exec */
#define F_GETFL 3 /* get file->f_flags */
#define F_SETFL 4 /* set file->f_flags */
#ifndef F_GETLK
#define F_GETLK 5
#define F_SETLK 6
#define F_SETLKW 7
#endif
#ifndef F_SETOWN
#define F_SETOWN 8 /* for sockets. */
#define F_GETOWN 9 /* for sockets. */
#endif
#ifndef F_SETSIG
#define F_SETSIG 10 /* for sockets. */
#define F_GETSIG 11 /* for sockets. */
#endif
#if __BITS_PER_LONG == 32 || defined(__KERNEL__)
#ifndef F_GETLK64
#define F_GETLK64 12 /* using 'struct flock64' */
#define F_SETLK64 13
#define F_SETLKW64 14
#endif
#endif /* __BITS_PER_LONG == 32 || defined(__KERNEL__) */
#ifndef F_SETOWN_EX
#define F_SETOWN_EX 15
#define F_GETOWN_EX 16
#endif
#ifndef F_GETOWNER_UIDS
#define F_GETOWNER_UIDS 17
#endif
/*
* Open File Description Locks
*
* Usually record locks held by a process are released on *any* close and are
* not inherited across a fork().
*
* These cmd values will set locks that conflict with process-associated
* record locks, but are "owned" by the open file description, not the
* process. This means that they are inherited across fork() like BSD (flock)
* locks, and they are only released automatically when the last reference to
* the open file against which they were acquired is put.
*/
#define F_OFD_GETLK 36
#define F_OFD_SETLK 37
#define F_OFD_SETLKW 38
#define F_OWNER_TID 0
#define F_OWNER_PID 1
#define F_OWNER_PGRP 2
struct f_owner_ex {
int type;
__kernel_pid_t pid;
};
/* for F_[GET|SET]FL */
#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
/* for posix fcntl() and lockf() */
#ifndef F_RDLCK
#define F_RDLCK 0
#define F_WRLCK 1
#define F_UNLCK 2
#endif
/* for old implementation of bsd flock () */
#ifndef F_EXLCK
#define F_EXLCK 4 /* or 3 */
#define F_SHLCK 8 /* or 4 */
#endif
/* operations for bsd flock(), also used by the kernel implementation */
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
#define LOCK_NB 4 /* or'd with one of the above to prevent
blocking */
#define LOCK_UN 8 /* remove lock */
/*
* LOCK_MAND support has been removed from the kernel. We leave the symbols
* here to not break legacy builds, but these should not be used in new code.
*/
#define LOCK_MAND 32 /* This is a mandatory flock ... */
#define LOCK_READ 64 /* which allows concurrent read operations */
#define LOCK_WRITE 128 /* which allows concurrent write operations */
#define LOCK_RW 192 /* which allows concurrent read & write ops */
#define F_LINUX_SPECIFIC_BASE 1024
#ifndef HAVE_ARCH_STRUCT_FLOCK
struct flock {
short l_type;
short l_whence;
__kernel_off_t l_start;
__kernel_off_t l_len;
__kernel_pid_t l_pid;
#ifdef __ARCH_FLOCK_EXTRA_SYSID
__ARCH_FLOCK_EXTRA_SYSID
#endif
#ifdef __ARCH_FLOCK_PAD
__ARCH_FLOCK_PAD
#endif
};
struct flock64 {
short l_type;
short l_whence;
__kernel_loff_t l_start;
__kernel_loff_t l_len;
__kernel_pid_t l_pid;
#ifdef __ARCH_FLOCK64_PAD
__ARCH_FLOCK64_PAD
#endif
};
#endif /* HAVE_ARCH_STRUCT_FLOCK */
#endif /* _ASM_GENERIC_FCNTL_H */

15
tools/include/uapi/linux/bits.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/* bits.h: Macros for dealing with bitmasks. */
#ifndef _UAPI_LINUX_BITS_H
#define _UAPI_LINUX_BITS_H
#define __GENMASK(h, l) \
(((~_UL(0)) - (_UL(1) << (l)) + 1) & \
(~_UL(0) >> (__BITS_PER_LONG - 1 - (h))))
#define __GENMASK_ULL(h, l) \
(((~_ULL(0)) - (_ULL(1) << (l)) + 1) & \
(~_ULL(0) >> (__BITS_PER_LONG_LONG - 1 - (h))))
#endif /* _UAPI_LINUX_BITS_H */

43
tools/include/uapi/linux/openat2.h
View File

@ -1,43 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _UAPI_LINUX_OPENAT2_H
#define _UAPI_LINUX_OPENAT2_H
#include <linux/types.h>
/*
* Arguments for how openat2(2) should open the target path. If only @flags and
* @mode are non-zero, then openat2(2) operates very similarly to openat(2).
*
* However, unlike openat(2), unknown or invalid bits in @flags result in
* -EINVAL rather than being silently ignored. @mode must be zero unless one of
* {O_CREAT, O_TMPFILE} are set.
*
* @flags: O_* flags.
* @mode: O_CREAT/O_TMPFILE file mode.
* @resolve: RESOLVE_* flags.
*/
struct open_how {
__u64 flags;
__u64 mode;
__u64 resolve;
};
/* how->resolve flags for openat2(2). */
#define RESOLVE_NO_XDEV 0x01 /* Block mount-point crossings
(includes bind-mounts). */
#define RESOLVE_NO_MAGICLINKS 0x02 /* Block traversal through procfs-style
"magic-links". */
#define RESOLVE_NO_SYMLINKS 0x04 /* Block traversal through all symlinks
(implies OEXT_NO_MAGICLINKS) */
#define RESOLVE_BENEATH 0x08 /* Block "lexical" trickery like
"..", symlinks, and absolute
paths which escape the dirfd. */
#define RESOLVE_IN_ROOT 0x10 /* Make all jumps to "/" and ".."
be scoped inside the dirfd
(similar to chroot(2)). */
#define RESOLVE_CACHED 0x20 /* Only complete if resolution can be
completed through cached lookup. May
return -EAGAIN if that's not
possible. */
#endif /* _UAPI_LINUX_OPENAT2_H */

33
tools/lib/perf/cpumap.c
View File

@ -18,9 +18,13 @@ void perf_cpu_map__set_nr(struct perf_cpu_map *map, int nr_cpus)
struct perf_cpu_map *perf_cpu_map__alloc(int nr_cpus)
{
RC_STRUCT(perf_cpu_map) *cpus = malloc(sizeof(*cpus) + sizeof(struct perf_cpu) * nr_cpus);
RC_STRUCT(perf_cpu_map) *cpus;
struct perf_cpu_map *result;
if (nr_cpus == 0)
return NULL;
cpus = malloc(sizeof(*cpus) + sizeof(struct perf_cpu) * nr_cpus);
if (ADD_RC_CHK(result, cpus)) {
cpus->nr = nr_cpus;
refcount_set(&cpus->refcnt, 1);
@ -316,6 +320,19 @@ bool perf_cpu_map__has_any_cpu_or_is_empty(const struct perf_cpu_map *map)
return map ? __perf_cpu_map__cpu(map, 0).cpu == -1 : true;
}
bool perf_cpu_map__is_any_cpu_or_is_empty(const struct perf_cpu_map *map)
{
if (!map)
return true;
return __perf_cpu_map__nr(map) == 1 && __perf_cpu_map__cpu(map, 0).cpu == -1;
}
bool perf_cpu_map__is_empty(const struct perf_cpu_map *map)
{
return map == NULL;
}
int perf_cpu_map__idx(const struct perf_cpu_map *cpus, struct perf_cpu cpu)
{
int low, high;
@ -372,6 +389,20 @@ bool perf_cpu_map__has_any_cpu(const struct perf_cpu_map *map)
return map && __perf_cpu_map__cpu(map, 0).cpu == -1;
}
struct perf_cpu perf_cpu_map__min(const struct perf_cpu_map *map)
{
struct perf_cpu cpu, result = {
.cpu = -1
};
int idx;
perf_cpu_map__for_each_cpu_skip_any(cpu, idx, map) {
result = cpu;
break;
}
return result;
}
struct perf_cpu perf_cpu_map__max(const struct perf_cpu_map *map)
{
struct perf_cpu result = {

16
tools/lib/perf/include/perf/cpumap.h
View File

@ -61,6 +61,22 @@ LIBPERF_API int perf_cpu_map__nr(const struct perf_cpu_map *cpus);
* perf_cpu_map__has_any_cpu_or_is_empty - is map either empty or has the "any CPU"/dummy value.
*/
LIBPERF_API bool perf_cpu_map__has_any_cpu_or_is_empty(const struct perf_cpu_map *map);
/**
* perf_cpu_map__is_any_cpu_or_is_empty - is map either empty or the "any CPU"/dummy value.
*/
LIBPERF_API bool perf_cpu_map__is_any_cpu_or_is_empty(const struct perf_cpu_map *map);
/**
* perf_cpu_map__is_empty - does the map contain no values and it doesn't
* contain the special "any CPU"/dummy value.
*/
LIBPERF_API bool perf_cpu_map__is_empty(const struct perf_cpu_map *map);
/**
* perf_cpu_map__min - the minimum CPU value or -1 if empty or just the "any CPU"/dummy value.
*/
LIBPERF_API struct perf_cpu perf_cpu_map__min(const struct perf_cpu_map *map);
/**
* perf_cpu_map__max - the maximum CPU value or -1 if empty or just the "any CPU"/dummy value.
*/
LIBPERF_API struct perf_cpu perf_cpu_map__max(const struct perf_cpu_map *map);
LIBPERF_API bool perf_cpu_map__has(const struct perf_cpu_map *map, struct perf_cpu cpu);
LIBPERF_API bool perf_cpu_map__equal(const struct perf_cpu_map *lhs,

4
tools/lib/perf/libperf.map
View File

@ -10,6 +10,10 @@ LIBPERF_0.0.1 {
perf_cpu_map__nr;
perf_cpu_map__cpu;
perf_cpu_map__has_any_cpu_or_is_empty;
perf_cpu_map__is_any_cpu_or_is_empty;
perf_cpu_map__is_empty;
perf_cpu_map__has_any_cpu;
perf_cpu_map__min;
perf_cpu_map__max;
perf_cpu_map__has;
perf_thread_map__new_array;

2
tools/lib/perf/mmap.c
View File

@ -279,7 +279,7 @@ union perf_event *perf_mmap__read_event(struct perf_mmap *map)
if (!refcount_read(&map->refcnt))
return NULL;
/* non-overwirte doesn't pause the ringbuffer */
/* non-overwrite doesn't pause the ringbuffer */
if (!map->overwrite)
map->end = perf_mmap__read_head(map);

40
tools/lib/subcmd/parse-options.c
View File

@ -633,11 +633,10 @@ int parse_options_subcommand(int argc, const char **argv, const struct option *o
const char *const subcommands[], const char *usagestr[], int flags)
{
struct parse_opt_ctx_t ctx;
char *buf = NULL;
/* build usage string if it's not provided */
if (subcommands && !usagestr[0]) {
char *buf = NULL;
astrcatf(&buf, "%s %s [<options>] {", subcmd_config.exec_name, argv[0]);
for (int i = 0; subcommands[i]; i++) {
@ -679,7 +678,10 @@ int parse_options_subcommand(int argc, const char **argv, const struct option *o
astrcatf(&error_buf, "unknown switch `%c'", *ctx.opt);
usage_with_options(usagestr, options);
}
if (buf) {
usagestr[0] = NULL;
free(buf);
}
return parse_options_end(&ctx);
}
@ -806,18 +808,30 @@ static int option__cmp(const void *va, const void *vb)
static struct option *options__order(const struct option *opts)
{
int nr_opts = 0, nr_group = 0, len;
const struct option *o = opts;
struct option *opt, *ordered, *group;
int nr_opts = 0, nr_group = 0, nr_parent = 0, len;
const struct option *o, *p = opts;
struct option *opt, *ordered = NULL, *group;
for (o = opts; o->type != OPTION_END; o++)
++nr_opts;
/* flatten the options that have parents */
for (p = opts; p != NULL; p = o->parent) {
for (o = p; o->type != OPTION_END; o++)
++nr_opts;
len = sizeof(*o) * (nr_opts + 1);
ordered = malloc(len);
if (!ordered)
goto out;
memcpy(ordered, opts, len);
/*
* the length is given by the number of options plus a null
* terminator for the last loop iteration.
*/
len = sizeof(*o) * (nr_opts + !o->parent);
group = realloc(ordered, len);
if (!group)
goto out;
ordered = group;
memcpy(&ordered[nr_parent], p, sizeof(*o) * (nr_opts - nr_parent));
nr_parent = nr_opts;
}
/* copy the last OPTION_END */
memcpy(&ordered[nr_opts], o, sizeof(*o));
/* sort each option group individually */
for (opt = group = ordered; opt->type != OPTION_END; opt++) {

70
tools/lib/subcmd/run-command.c
View File

@ -165,43 +165,65 @@ int start_command(struct child_process *cmd)
return 0;
}
static int wait_or_whine(pid_t pid)
static int wait_or_whine(struct child_process *cmd, bool block)
{
char sbuf[STRERR_BUFSIZE];
bool finished = cmd->finished;
int result = cmd->finish_result;
for (;;) {
while (!finished) {
int status, code;
pid_t waiting = waitpid(pid, &status, 0);
pid_t waiting = waitpid(cmd->pid, &status, block ? 0 : WNOHANG);
if (!block && waiting == 0)
break;
if (waiting < 0 && errno == EINTR)
continue;
finished = true;
if (waiting < 0) {
if (errno == EINTR)
continue;
char sbuf[STRERR_BUFSIZE];
fprintf(stderr, " Error: waitpid failed (%s)",
str_error_r(errno, sbuf, sizeof(sbuf)));
return -ERR_RUN_COMMAND_WAITPID;
}
if (waiting != pid)
return -ERR_RUN_COMMAND_WAITPID_WRONG_PID;
if (WIFSIGNALED(status))
return -ERR_RUN_COMMAND_WAITPID_SIGNAL;
if (!WIFEXITED(status))
return -ERR_RUN_COMMAND_WAITPID_NOEXIT;
code = WEXITSTATUS(status);
switch (code) {
case 127:
return -ERR_RUN_COMMAND_EXEC;
case 0:
return 0;
default:
return -code;
result = -ERR_RUN_COMMAND_WAITPID;
} else if (waiting != cmd->pid) {
result = -ERR_RUN_COMMAND_WAITPID_WRONG_PID;
} else if (WIFSIGNALED(status)) {
result = -ERR_RUN_COMMAND_WAITPID_SIGNAL;
} else if (!WIFEXITED(status)) {
result = -ERR_RUN_COMMAND_WAITPID_NOEXIT;
} else {
code = WEXITSTATUS(status);
switch (code) {
case 127:
result = -ERR_RUN_COMMAND_EXEC;
break;
case 0:
result = 0;
break;
default:
result = -code;
break;
}
}
}
if (finished) {
cmd->finished = 1;
cmd->finish_result = result;
}
return result;
}
int check_if_command_finished(struct child_process *cmd)
{
wait_or_whine(cmd, /*block=*/false);
return cmd->finished;
}
int finish_command(struct child_process *cmd)
{
return wait_or_whine(cmd->pid);
return wait_or_whine(cmd, /*block=*/true);
}
int run_command(struct child_process *cmd)

3
tools/lib/subcmd/run-command.h
View File

@ -41,17 +41,20 @@ struct child_process {
int err;
const char *dir;
const char *const *env;
int finish_result;
unsigned no_stdin:1;
unsigned no_stdout:1;
unsigned no_stderr:1;
unsigned exec_cmd:1; /* if this is to be external sub-command */
unsigned stdout_to_stderr:1;
unsigned finished:1;
void (*preexec_cb)(void);
/* If set, call function in child rather than doing an exec. */
int (*no_exec_cmd)(struct child_process *process);
};
int start_command(struct child_process *);
int check_if_command_finished(struct child_process *);
int finish_command(struct child_process *);
int run_command(struct child_process *);

14
tools/perf/Build
View File

@ -59,3 +59,17 @@ perf-y += ui/
perf-y += scripts/
gtk-y += ui/gtk/
ifdef SHELLCHECK
SHELL_TESTS := $(wildcard *.sh)
TEST_LOGS := $(SHELL_TESTS:%=%.shellcheck_log)
else
SHELL_TESTS :=
TEST_LOGS :=
endif
$(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -s bash -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
perf-y += $(TEST_LOGS)

12
tools/perf/Documentation/perf-arm-spe.txt
View File

@ -116,6 +116,15 @@ Depending on CPU model, the kernel may need to be booted with page table isolati
(kpti=off). If KPTI needs to be disabled, this will fail with a console message "profiling buffer
inaccessible. Try passing 'kpti=off' on the kernel command line".
For the full criteria that determine whether KPTI needs to be forced off or not, see function
unmap_kernel_at_el0() in the kernel sources. Common cases where it's not required
are on the CPUs in kpti_safe_list, or on Arm v8.5+ where FEAT_E0PD is mandatory.
The SPE interrupt must also be described by the firmware. If the module is loaded and KPTI is
disabled (or isn't required to be disabled) but the SPE PMU still doesn't show in
/sys/bus/event_source/devices/, then it's possible that the SPE interrupt isn't described by
ACPI or DT. In this case no warning will be printed by the driver.
Capturing SPE with perf command-line tools
------------------------------------------
@ -199,7 +208,8 @@ Common errors
- "Cannot find PMU `arm_spe'. Missing kernel support?"
Module not built or loaded, KPTI not disabled (see above), or running on a VM
Module not built or loaded, KPTI not disabled, interrupt not described by firmware,
or running on a VM. See 'Kernel Requirements' above.
- "Arm SPE CONTEXT packets not found in the traces."

1
tools/perf/Documentation/perf-list.txt
View File

@ -71,6 +71,7 @@ counted. The following modifiers exist:
D - pin the event to the PMU
W - group is weak and will fallback to non-group if not schedulable,
e - group or event are exclusive and do not share the PMU
b - use BPF aggregration (see perf stat --bpf-counters)
The 'p' modifier can be used for specifying how precise the instruction
address should be. The 'p' modifier can be specified multiple times:

9
tools/perf/Documentation/perf-report.txt
View File

@ -121,6 +121,9 @@ OPTIONS
- type: Data type of sample memory access.
- typeoff: Offset in the data type of sample memory access.
- symoff: Offset in the symbol.
- weight1: Average value of event specific weight (1st field of weight_struct).
- weight2: Average value of event specific weight (2nd field of weight_struct).
- weight3: Average value of event specific weight (3rd field of weight_struct).
By default, comm, dso and symbol keys are used.
(i.e. --sort comm,dso,symbol)
@ -198,7 +201,11 @@ OPTIONS
--fields=::
Specify output field - multiple keys can be specified in CSV format.
Following fields are available:
overhead, overhead_sys, overhead_us, overhead_children, sample and period.
overhead, overhead_sys, overhead_us, overhead_children, sample, period,
weight1, weight2, weight3, ins_lat, p_stage_cyc and retire_lat. The
last 3 names are alias for the corresponding weights. When the weight
fields are used, they will show the average value of the weight.
Also it can contain any sort key(s).
By default, every sort keys not specified in -F will be appended

36
tools/perf/Documentation/perf-sched.txt
View File

@ -20,6 +20,26 @@ There are several variants of 'perf sched':
'perf sched latency' to report the per task scheduling latencies
and other scheduling properties of the workload.
Example usage:
perf sched record -- sleep 1
perf sched latency
-------------------------------------------------------------------------------------------------------------------------------------------
Task | Runtime ms | Count | Avg delay ms | Max delay ms | Max delay start | Max delay end |
-------------------------------------------------------------------------------------------------------------------------------------------
perf:(2) | 2.804 ms | 66 | avg: 0.524 ms | max: 1.069 ms | max start: 254752.314960 s | max end: 254752.316029 s
NetworkManager:1343 | 0.372 ms | 13 | avg: 0.008 ms | max: 0.013 ms | max start: 254751.551153 s | max end: 254751.551166 s
kworker/1:2-xfs:4649 | 0.012 ms | 1 | avg: 0.008 ms | max: 0.008 ms | max start: 254751.519807 s | max end: 254751.519815 s
kworker/3:1-xfs:388 | 0.011 ms | 1 | avg: 0.006 ms | max: 0.006 ms | max start: 254751.519809 s | max end: 254751.519815 s
sleep:147736 | 0.938 ms | 3 | avg: 0.006 ms | max: 0.007 ms | max start: 254751.313817 s | max end: 254751.313824 s
It shows Runtime(time that a task spent actually running on the CPU),
Count(number of times a delay was calculated) and delay(time that a
task was ready to run but was kept waiting).
Tasks with the same command name are merged and the merge count is
given within (), However if -p option is used, pid is mentioned.
'perf sched script' to see a detailed trace of the workload that
was recorded (aliased to 'perf script' for now).
@ -78,6 +98,22 @@ OPTIONS
--force::
Don't complain, do it.
OPTIONS for 'perf sched latency'
-------------------------------
-C::
--CPU <n>::
CPU to profile on.
-p::
--pids::
latency stats per pid instead of per command name.
-s::
--sort <key[,key2...]>::
sort by key(s): runtime, switch, avg, max
by default it's sorted by "avg ,max ,switch ,runtime".
OPTIONS for 'perf sched map'
----------------------------

7
tools/perf/Documentation/perf-script.txt
View File

@ -132,9 +132,9 @@ OPTIONS
Comma separated list of fields to print. Options are:
comm, tid, pid, time, cpu, event, trace, ip, sym, dso, dsoff, addr, symoff,
srcline, period, iregs, uregs, brstack, brstacksym, flags, bpf-output,
brstackinsn, brstackinsnlen, brstackoff, callindent, insn, disasm,
brstackinsn, brstackinsnlen, brstackdisasm, brstackoff, callindent, insn, disasm,
insnlen, synth, phys_addr, metric, misc, srccode, ipc, data_page_size,
code_page_size, ins_lat, machine_pid, vcpu, cgroup, retire_lat.
code_page_size, ins_lat, machine_pid, vcpu, cgroup, retire_lat,
Field list can be prepended with the type, trace, sw or hw,
to indicate to which event type the field list applies.
@ -257,6 +257,9 @@ OPTIONS
can’t know the next sequential instruction after an unconditional branch unless
you calculate that based on its length.
brstackdisasm acts like brstackinsn, but will print disassembled instructions if
perf is built with the capstone library.
The brstackoff field will print an offset into a specific dso/binary.
With the metric option perf script can compute metrics for

13
tools/perf/Documentation/perf-test.txt
View File

@ -31,9 +31,20 @@ OPTIONS
--verbose::
Be more verbose.
-S::
--sequential::
Run tests one after the other, this is the default mode.
-p::
--parallel::
Run tests in parallel, speeds up the whole process but is not safe with
the current infrastructure, where some tests that compete for some resources,
for instance, 'perf probe' tests that add/remove probes or clean all probes, etc.
-F::
--dont-fork::
Do not fork child for each test, run all tests within single process.
Do not fork child for each test, run all tests within single process, this
sets sequential mode.
--dso::
Specify a DSO for the "Symbols" test.

25
tools/perf/Makefile.config
View File

@ -182,6 +182,16 @@ endif
FEATURE_CHECK_CFLAGS-libzstd := $(LIBZSTD_CFLAGS)
FEATURE_CHECK_LDFLAGS-libzstd := $(LIBZSTD_LDFLAGS)
# for linking with debug library, run like:
# make DEBUG=1 LIBTRACEEVENT_DIR=/opt/libtraceevent/
TRACEEVENTLIBS := -ltraceevent
ifdef LIBTRACEEVENT_DIR
LIBTRACEEVENT_CFLAGS := -I$(LIBTRACEEVENT_DIR)/include
LIBTRACEEVENT_LDFLAGS := -L$(LIBTRACEEVENT_DIR)/lib
endif
FEATURE_CHECK_CFLAGS-libtraceevent := $(LIBTRACEEVENT_CFLAGS)
FEATURE_CHECK_LDFLAGS-libtraceevent := $(LIBTRACEEVENT_LDFLAGS) $(TRACEEVENTLIBS)
FEATURE_CHECK_CFLAGS-bpf = -I. -I$(srctree)/tools/include -I$(srctree)/tools/arch/$(SRCARCH)/include/uapi -I$(srctree)/tools/include/uapi
# include ARCH specific config
-include $(src-perf)/arch/$(SRCARCH)/Makefile
@ -486,7 +496,10 @@ ifdef NO_DWARF
endif
ifeq ($(feature-scandirat), 1)
CFLAGS += -DHAVE_SCANDIRAT_SUPPORT
# Ignore having scandirat with memory sanitizer that lacks an interceptor.
ifeq ($(filter s% -fsanitize=memory%,$(EXTRA_CFLAGS),),)
CFLAGS += -DHAVE_SCANDIRAT_SUPPORT
endif
endif
ifeq ($(feature-sched_getcpu), 1)
@ -1165,9 +1178,10 @@ endif
ifneq ($(NO_LIBTRACEEVENT),1)
$(call feature_check,libtraceevent)
ifeq ($(feature-libtraceevent), 1)
CFLAGS += -DHAVE_LIBTRACEEVENT
EXTLIBS += -ltraceevent
LIBTRACEEVENT_VERSION := $(shell $(PKG_CONFIG) --modversion libtraceevent)
CFLAGS += -DHAVE_LIBTRACEEVENT $(LIBTRACEEVENT_CFLAGS)
LDFLAGS += $(LIBTRACEEVENT_LDFLAGS)
EXTLIBS += ${TRACEEVENTLIBS}
LIBTRACEEVENT_VERSION := $(shell PKG_CONFIG_PATH=$(LIBTRACEEVENT_DIR) $(PKG_CONFIG) --modversion libtraceevent)
LIBTRACEEVENT_VERSION_1 := $(word 1, $(subst ., ,$(LIBTRACEEVENT_VERSION)))
LIBTRACEEVENT_VERSION_2 := $(word 2, $(subst ., ,$(LIBTRACEEVENT_VERSION)))
LIBTRACEEVENT_VERSION_3 := $(word 3, $(subst ., ,$(LIBTRACEEVENT_VERSION)))
@ -1175,7 +1189,7 @@ ifneq ($(NO_LIBTRACEEVENT),1)
CFLAGS += -DLIBTRACEEVENT_VERSION=$(LIBTRACEEVENT_VERSION_CPP)
$(call detected,CONFIG_LIBTRACEEVENT)
else
$(error ERROR: libtraceevent is missing. Please install libtraceevent-dev/libtraceevent-devel or build with NO_LIBTRACEEVENT=1)
$(error ERROR: libtraceevent is missing. Please install libtraceevent-dev/libtraceevent-devel and/or set LIBTRACEEVENT_DIR or build with NO_LIBTRACEEVENT=1)
endif
$(call feature_check,libtracefs)
@ -1301,6 +1315,7 @@ ifeq ($(VF),1)
$(call print_var,LIBUNWIND_DIR)
$(call print_var,LIBDW_DIR)
$(call print_var,JDIR)
$(call print_var,LIBTRACEEVENT_DIR)
ifeq ($(dwarf-post-unwind),1)
$(call feature_print_text,"DWARF post unwind library", $(dwarf-post-unwind-text)) $(info $(MSG))

100
tools/perf/Makefile.perf
View File

@ -458,35 +458,53 @@ SHELL = $(SHELL_PATH)
arm64_gen_sysreg_dir := $(srctree)/tools/arch/arm64/tools
ifneq ($(OUTPUT),)
arm64_gen_sysreg_outdir := $(OUTPUT)
arm64_gen_sysreg_outdir := $(abspath $(OUTPUT))
else
arm64_gen_sysreg_outdir := $(CURDIR)
endif
arm64-sysreg-defs: FORCE
$(Q)$(MAKE) -C $(arm64_gen_sysreg_dir) O=$(arm64_gen_sysreg_outdir)
$(Q)$(MAKE) -C $(arm64_gen_sysreg_dir) O=$(arm64_gen_sysreg_outdir) \
prefix= subdir=
arm64-sysreg-defs-clean:
$(call QUIET_CLEAN,arm64-sysreg-defs)
$(Q)$(MAKE) -C $(arm64_gen_sysreg_dir) O=$(arm64_gen_sysreg_outdir) \
clean > /dev/null
prefix= subdir= clean > /dev/null
beauty_linux_dir := $(srctree)/tools/perf/trace/beauty/include/linux/
beauty_uapi_linux_dir := $(srctree)/tools/perf/trace/beauty/include/uapi/linux/
beauty_uapi_sound_dir := $(srctree)/tools/perf/trace/beauty/include/uapi/sound/
beauty_arch_asm_dir := $(srctree)/tools/perf/trace/beauty/arch/x86/include/asm/
beauty_x86_arch_asm_uapi_dir := $(srctree)/tools/perf/trace/beauty/arch/x86/include/uapi/asm/
linux_uapi_dir := $(srctree)/tools/include/uapi/linux
asm_generic_uapi_dir := $(srctree)/tools/include/uapi/asm-generic
arch_asm_uapi_dir := $(srctree)/tools/arch/$(SRCARCH)/include/uapi/asm/
x86_arch_asm_uapi_dir := $(srctree)/tools/arch/x86/include/uapi/asm/
x86_arch_asm_dir := $(srctree)/tools/arch/x86/include/asm/
beauty_outdir := $(OUTPUT)trace/beauty/generated
beauty_ioctl_outdir := $(beauty_outdir)/ioctl
drm_ioctl_array := $(beauty_ioctl_outdir)/drm_ioctl_array.c
drm_hdr_dir := $(srctree)/tools/include/uapi/drm
drm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/drm_ioctl.sh
# Create output directory if not already present
$(shell [ -d '$(beauty_ioctl_outdir)' ] || mkdir -p '$(beauty_ioctl_outdir)')
fs_at_flags_array := $(beauty_outdir)/fs_at_flags_array.c
fs_at_flags_tbl := $(srctree)/tools/perf/trace/beauty/fs_at_flags.sh
$(fs_at_flags_array): $(beauty_uapi_linux_dir)/fcntl.h $(fs_at_flags_tbl)
$(Q)$(SHELL) '$(fs_at_flags_tbl)' $(beauty_uapi_linux_dir) > $@
clone_flags_array := $(beauty_outdir)/clone_flags_array.c
clone_flags_tbl := $(srctree)/tools/perf/trace/beauty/clone.sh
$(clone_flags_array): $(beauty_uapi_linux_dir)/sched.h $(clone_flags_tbl)
$(Q)$(SHELL) '$(clone_flags_tbl)' $(beauty_uapi_linux_dir) > $@
drm_ioctl_array := $(beauty_ioctl_outdir)/drm_ioctl_array.c
drm_hdr_dir := $(srctree)/tools/include/uapi/drm
drm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/drm_ioctl.sh
$(drm_ioctl_array): $(drm_hdr_dir)/drm.h $(drm_hdr_dir)/i915_drm.h $(drm_ioctl_tbl)
$(Q)$(SHELL) '$(drm_ioctl_tbl)' $(drm_hdr_dir) > $@
@ -499,20 +517,20 @@ $(fadvise_advice_array): $(linux_uapi_dir)/in.h $(fadvise_advice_tbl)
fsmount_arrays := $(beauty_outdir)/fsmount_arrays.c
fsmount_tbls := $(srctree)/tools/perf/trace/beauty/fsmount.sh
$(fsmount_arrays): $(linux_uapi_dir)/fs.h $(fsmount_tbls)
$(Q)$(SHELL) '$(fsmount_tbls)' $(linux_uapi_dir) > $@
$(fsmount_arrays): $(beauty_uapi_linux_dir)/mount.h $(fsmount_tbls)
$(Q)$(SHELL) '$(fsmount_tbls)' $(beauty_uapi_linux_dir) > $@
fspick_arrays := $(beauty_outdir)/fspick_arrays.c
fspick_tbls := $(srctree)/tools/perf/trace/beauty/fspick.sh
$(fspick_arrays): $(linux_uapi_dir)/fs.h $(fspick_tbls)
$(Q)$(SHELL) '$(fspick_tbls)' $(linux_uapi_dir) > $@
$(fspick_arrays): $(beauty_uapi_linux_dir)/mount.h $(fspick_tbls)
$(Q)$(SHELL) '$(fspick_tbls)' $(beauty_uapi_linux_dir) > $@
fsconfig_arrays := $(beauty_outdir)/fsconfig_arrays.c
fsconfig_tbls := $(srctree)/tools/perf/trace/beauty/fsconfig.sh
$(fsconfig_arrays): $(linux_uapi_dir)/fs.h $(fsconfig_tbls)
$(Q)$(SHELL) '$(fsconfig_tbls)' $(linux_uapi_dir) > $@
$(fsconfig_arrays): $(beauty_uapi_linux_dir)/mount.h $(fsconfig_tbls)
$(Q)$(SHELL) '$(fsconfig_tbls)' $(beauty_uapi_linux_dir) > $@
pkey_alloc_access_rights_array := $(beauty_outdir)/pkey_alloc_access_rights_array.c
asm_generic_hdr_dir := $(srctree)/tools/include/uapi/asm-generic/
@ -525,15 +543,15 @@ sndrv_ctl_ioctl_array := $(beauty_ioctl_outdir)/sndrv_ctl_ioctl_array.c
sndrv_ctl_hdr_dir := $(srctree)/tools/include/uapi/sound
sndrv_ctl_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/sndrv_ctl_ioctl.sh
$(sndrv_ctl_ioctl_array): $(sndrv_ctl_hdr_dir)/asound.h $(sndrv_ctl_ioctl_tbl)
$(Q)$(SHELL) '$(sndrv_ctl_ioctl_tbl)' $(sndrv_ctl_hdr_dir) > $@
$(sndrv_ctl_ioctl_array): $(beauty_uapi_sound_dir)/asound.h $(sndrv_ctl_ioctl_tbl)
$(Q)$(SHELL) '$(sndrv_ctl_ioctl_tbl)' $(beauty_uapi_sound_dir) > $@
sndrv_pcm_ioctl_array := $(beauty_ioctl_outdir)/sndrv_pcm_ioctl_array.c
sndrv_pcm_hdr_dir := $(srctree)/tools/include/uapi/sound
sndrv_pcm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/sndrv_pcm_ioctl.sh
$(sndrv_pcm_ioctl_array): $(sndrv_pcm_hdr_dir)/asound.h $(sndrv_pcm_ioctl_tbl)
$(Q)$(SHELL) '$(sndrv_pcm_ioctl_tbl)' $(sndrv_pcm_hdr_dir) > $@
$(sndrv_pcm_ioctl_array): $(beauty_uapi_sound_dir)/asound.h $(sndrv_pcm_ioctl_tbl)
$(Q)$(SHELL) '$(sndrv_pcm_ioctl_tbl)' $(beauty_uapi_sound_dir) > $@
kcmp_type_array := $(beauty_outdir)/kcmp_type_array.c
kcmp_hdr_dir := $(srctree)/tools/include/uapi/linux/
@ -562,11 +580,10 @@ $(sockaddr_arrays): $(beauty_linux_dir)/socket.h $(sockaddr_tbl)
$(Q)$(SHELL) '$(sockaddr_tbl)' $(beauty_linux_dir) > $@
vhost_virtio_ioctl_array := $(beauty_ioctl_outdir)/vhost_virtio_ioctl_array.c
vhost_virtio_hdr_dir := $(srctree)/tools/include/uapi/linux
vhost_virtio_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/vhost_virtio_ioctl.sh
$(vhost_virtio_ioctl_array): $(vhost_virtio_hdr_dir)/vhost.h $(vhost_virtio_ioctl_tbl)
$(Q)$(SHELL) '$(vhost_virtio_ioctl_tbl)' $(vhost_virtio_hdr_dir) > $@
$(vhost_virtio_ioctl_array): $(beauty_uapi_linux_dir)/vhost.h $(vhost_virtio_ioctl_tbl)
$(Q)$(SHELL) '$(vhost_virtio_ioctl_tbl)' $(beauty_uapi_linux_dir) > $@
perf_ioctl_array := $(beauty_ioctl_outdir)/perf_ioctl_array.c
perf_hdr_dir := $(srctree)/tools/include/uapi/linux
@ -597,15 +614,14 @@ $(mremap_flags_array): $(linux_uapi_dir)/mman.h $(mremap_flags_tbl)
mount_flags_array := $(beauty_outdir)/mount_flags_array.c
mount_flags_tbl := $(srctree)/tools/perf/trace/beauty/mount_flags.sh
$(mount_flags_array): $(linux_uapi_dir)/fs.h $(mount_flags_tbl)
$(Q)$(SHELL) '$(mount_flags_tbl)' $(linux_uapi_dir) > $@
$(mount_flags_array): $(beauty_uapi_linux_dir)/mount.h $(mount_flags_tbl)
$(Q)$(SHELL) '$(mount_flags_tbl)' $(beauty_uapi_linux_dir) > $@
move_mount_flags_array := $(beauty_outdir)/move_mount_flags_array.c
move_mount_flags_tbl := $(srctree)/tools/perf/trace/beauty/move_mount_flags.sh
$(move_mount_flags_array): $(linux_uapi_dir)/fs.h $(move_mount_flags_tbl)
$(Q)$(SHELL) '$(move_mount_flags_tbl)' $(linux_uapi_dir) > $@
$(move_mount_flags_array): $(beauty_uapi_linux_dir)/mount.h $(move_mount_flags_tbl)
$(Q)$(SHELL) '$(move_mount_flags_tbl)' $(beauty_uapi_linux_dir) > $@
mmap_prot_array := $(beauty_outdir)/mmap_prot_array.c
mmap_prot_tbl := $(srctree)/tools/perf/trace/beauty/mmap_prot.sh
@ -614,29 +630,28 @@ $(mmap_prot_array): $(asm_generic_uapi_dir)/mman.h $(asm_generic_uapi_dir)/mman-
$(Q)$(SHELL) '$(mmap_prot_tbl)' $(asm_generic_uapi_dir) $(arch_asm_uapi_dir) > $@
prctl_option_array := $(beauty_outdir)/prctl_option_array.c
prctl_hdr_dir := $(srctree)/tools/include/uapi/linux/
prctl_option_tbl := $(srctree)/tools/perf/trace/beauty/prctl_option.sh
$(prctl_option_array): $(prctl_hdr_dir)/prctl.h $(prctl_option_tbl)
$(Q)$(SHELL) '$(prctl_option_tbl)' $(prctl_hdr_dir) > $@
$(prctl_option_array): $(beauty_uapi_linux_dir)/prctl.h $(prctl_option_tbl)
$(Q)$(SHELL) '$(prctl_option_tbl)' $(beauty_uapi_linux_dir) > $@
usbdevfs_ioctl_array := $(beauty_ioctl_outdir)/usbdevfs_ioctl_array.c
usbdevfs_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/usbdevfs_ioctl.sh
$(usbdevfs_ioctl_array): $(linux_uapi_dir)/usbdevice_fs.h $(usbdevfs_ioctl_tbl)
$(Q)$(SHELL) '$(usbdevfs_ioctl_tbl)' $(linux_uapi_dir) > $@
$(usbdevfs_ioctl_array): $(beauty_uapi_linux_dir)/usbdevice_fs.h $(usbdevfs_ioctl_tbl)
$(Q)$(SHELL) '$(usbdevfs_ioctl_tbl)' $(beauty_uapi_linux_dir) > $@
x86_arch_prctl_code_array := $(beauty_outdir)/x86_arch_prctl_code_array.c
x86_arch_prctl_code_tbl := $(srctree)/tools/perf/trace/beauty/x86_arch_prctl.sh
$(x86_arch_prctl_code_array): $(x86_arch_asm_uapi_dir)/prctl.h $(x86_arch_prctl_code_tbl)
$(Q)$(SHELL) '$(x86_arch_prctl_code_tbl)' $(x86_arch_asm_uapi_dir) > $@
$(x86_arch_prctl_code_array): $(beauty_x86_arch_asm_uapi_dir)/prctl.h $(x86_arch_prctl_code_tbl)
$(Q)$(SHELL) '$(x86_arch_prctl_code_tbl)' $(beauty_x86_arch_asm_uapi_dir) > $@
x86_arch_irq_vectors_array := $(beauty_outdir)/x86_arch_irq_vectors_array.c
x86_arch_irq_vectors_tbl := $(srctree)/tools/perf/trace/beauty/tracepoints/x86_irq_vectors.sh
$(x86_arch_irq_vectors_array): $(x86_arch_asm_dir)/irq_vectors.h $(x86_arch_irq_vectors_tbl)
$(Q)$(SHELL) '$(x86_arch_irq_vectors_tbl)' $(x86_arch_asm_dir) > $@
$(x86_arch_irq_vectors_array): $(beauty_arch_asm_dir)/irq_vectors.h $(x86_arch_irq_vectors_tbl)
$(Q)$(SHELL) '$(x86_arch_irq_vectors_tbl)' $(beauty_arch_asm_dir) > $@
x86_arch_MSRs_array := $(beauty_outdir)/x86_arch_MSRs_array.c
x86_arch_MSRs_tbl := $(srctree)/tools/perf/trace/beauty/tracepoints/x86_msr.sh
@ -647,8 +662,8 @@ $(x86_arch_MSRs_array): $(x86_arch_asm_dir)/msr-index.h $(x86_arch_MSRs_tbl)
rename_flags_array := $(beauty_outdir)/rename_flags_array.c
rename_flags_tbl := $(srctree)/tools/perf/trace/beauty/rename_flags.sh
$(rename_flags_array): $(linux_uapi_dir)/fs.h $(rename_flags_tbl)
$(Q)$(SHELL) '$(rename_flags_tbl)' $(linux_uapi_dir) > $@
$(rename_flags_array): $(beauty_uapi_linux_dir)/fs.h $(rename_flags_tbl)
$(Q)$(SHELL) '$(rename_flags_tbl)' $(beauty_uapi_linux_dir) > $@
arch_errno_name_array := $(beauty_outdir)/arch_errno_name_array.c
arch_errno_hdr_dir := $(srctree)/tools
@ -657,11 +672,17 @@ arch_errno_tbl := $(srctree)/tools/perf/trace/beauty/arch_errno_names.sh
$(arch_errno_name_array): $(arch_errno_tbl)
$(Q)$(SHELL) '$(arch_errno_tbl)' '$(patsubst -%,,$(CC))' $(arch_errno_hdr_dir) > $@
statx_mask_array := $(beauty_outdir)/statx_mask_array.c
statx_mask_tbl := $(srctree)/tools/perf/trace/beauty/statx_mask.sh
$(statx_mask_array): $(beauty_uapi_linux_dir)/stat.h $(statx_mask_tbl)
$(Q)$(SHELL) '$(statx_mask_tbl)' $(beauty_uapi_linux_dir) > $@
sync_file_range_arrays := $(beauty_outdir)/sync_file_range_arrays.c
sync_file_range_tbls := $(srctree)/tools/perf/trace/beauty/sync_file_range.sh
$(sync_file_range_arrays): $(linux_uapi_dir)/fs.h $(sync_file_range_tbls)
$(Q)$(SHELL) '$(sync_file_range_tbls)' $(linux_uapi_dir) > $@
$(sync_file_range_arrays): $(beauty_uapi_linux_dir)/fs.h $(sync_file_range_tbls)
$(Q)$(SHELL) '$(sync_file_range_tbls)' $(beauty_uapi_linux_dir) > $@
TESTS_CORESIGHT_DIR := $(srctree)/tools/perf/tests/shell/coresight
@ -762,6 +783,8 @@ build-dir = $(or $(__build-dir),.)
prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders \
arm64-sysreg-defs \
$(fs_at_flags_array) \
$(clone_flags_array) \
$(drm_ioctl_array) \
$(fadvise_advice_array) \
$(fsconfig_arrays) \
@ -789,6 +812,7 @@ prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders \
$(x86_arch_prctl_code_array) \
$(rename_flags_array) \
$(arch_errno_name_array) \
$(statx_mask_array) \
$(sync_file_range_arrays) \
$(LIBAPI) \
$(LIBPERF) \

387
tools/perf/arch/arm/util/cs-etm.c
View File

@ -66,18 +66,30 @@ static const char * const metadata_ete_ro[] = {
[CS_ETE_TS_SOURCE] = "ts_source",
};
static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu);
static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu);
enum cs_etm_version { CS_NOT_PRESENT, CS_ETMV3, CS_ETMV4, CS_ETE };
static int cs_etm_validate_context_id(struct auxtrace_record *itr,
struct evsel *evsel, int cpu)
static bool cs_etm_is_ete(struct perf_pmu *cs_etm_pmu, struct perf_cpu cpu);
static int cs_etm_get_ro(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path, __u64 *val);
static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path);
static enum cs_etm_version cs_etm_get_version(struct perf_pmu *cs_etm_pmu,
struct perf_cpu cpu)
{
if (cs_etm_is_ete(cs_etm_pmu, cpu))
return CS_ETE;
else if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]))
return CS_ETMV4;
else if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv3_ro[CS_ETM_ETMCCER]))
return CS_ETMV3;
return CS_NOT_PRESENT;
}
static int cs_etm_validate_context_id(struct perf_pmu *cs_etm_pmu, struct evsel *evsel,
struct perf_cpu cpu)
{
struct cs_etm_recording *ptr =
container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
char path[PATH_MAX];
int err;
u32 val;
__u64 val;
u64 contextid = evsel->core.attr.config &
(perf_pmu__format_bits(cs_etm_pmu, "contextid") |
perf_pmu__format_bits(cs_etm_pmu, "contextid1") |
@ -87,23 +99,16 @@ static int cs_etm_validate_context_id(struct auxtrace_record *itr,
return 0;
/* Not supported in etmv3 */
if (!cs_etm_is_etmv4(itr, cpu)) {
if (cs_etm_get_version(cs_etm_pmu, cpu) == CS_ETMV3) {
pr_err("%s: contextid not supported in ETMv3, disable with %s/contextid=0/\n",
CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME);
return -EINVAL;
}
/* Get a handle on TRCIDR2 */
snprintf(path, PATH_MAX, "cpu%d/%s",
cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR2]);
err = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);
/* There was a problem reading the file, bailing out */
if (err != 1) {
pr_err("%s: can't read file %s\n", CORESIGHT_ETM_PMU_NAME,
path);
err = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR2], &val);
if (err)
return err;
}
if (contextid &
perf_pmu__format_bits(cs_etm_pmu, "contextid1")) {
@ -140,37 +145,26 @@ static int cs_etm_validate_context_id(struct auxtrace_record *itr,
return 0;
}
static int cs_etm_validate_timestamp(struct auxtrace_record *itr,
struct evsel *evsel, int cpu)
static int cs_etm_validate_timestamp(struct perf_pmu *cs_etm_pmu, struct evsel *evsel,
struct perf_cpu cpu)
{
struct cs_etm_recording *ptr =
container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
char path[PATH_MAX];
int err;
u32 val;
__u64 val;
if (!(evsel->core.attr.config &
perf_pmu__format_bits(cs_etm_pmu, "timestamp")))
return 0;
if (!cs_etm_is_etmv4(itr, cpu)) {
if (cs_etm_get_version(cs_etm_pmu, cpu) == CS_ETMV3) {
pr_err("%s: timestamp not supported in ETMv3, disable with %s/timestamp=0/\n",
CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME);
return -EINVAL;
}
/* Get a handle on TRCIRD0 */
snprintf(path, PATH_MAX, "cpu%d/%s",
cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);
err = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);
/* There was a problem reading the file, bailing out */
if (err != 1) {
pr_err("%s: can't read file %s\n",
CORESIGHT_ETM_PMU_NAME, path);
err = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0], &val);
if (err)
return err;
}
/*
* TRCIDR0.TSSIZE, bit [28-24], indicates whether global timestamping
@ -187,6 +181,13 @@ static int cs_etm_validate_timestamp(struct auxtrace_record *itr,
return 0;
}
static struct perf_pmu *cs_etm_get_pmu(struct auxtrace_record *itr)
{
struct cs_etm_recording *ptr = container_of(itr, struct cs_etm_recording, itr);
return ptr->cs_etm_pmu;
}
/*
* Check whether the requested timestamp and contextid options should be
* available on all requested CPUs and if not, tell the user how to override.
@ -194,41 +195,45 @@ static int cs_etm_validate_timestamp(struct auxtrace_record *itr,
* first is better. In theory the kernel could still disable the option for
* some other reason so this is best effort only.
*/
static int cs_etm_validate_config(struct auxtrace_record *itr,
static int cs_etm_validate_config(struct perf_pmu *cs_etm_pmu,
struct evsel *evsel)
{
int i, err = -EINVAL;
int idx, err = 0;
struct perf_cpu_map *event_cpus = evsel->evlist->core.user_requested_cpus;
struct perf_cpu_map *online_cpus = perf_cpu_map__new_online_cpus();
struct perf_cpu_map *intersect_cpus;
struct perf_cpu cpu;
/* Set option of each CPU we have */
for (i = 0; i < cpu__max_cpu().cpu; i++) {
struct perf_cpu cpu = { .cpu = i, };
/*
* Set option of each CPU we have. In per-cpu case, do the validation
* for CPUs to work with. In per-thread case, the CPU map has the "any"
* CPU value. Since the traced program can run on any CPUs in this case,
* thus don't skip validation.
*/
if (!perf_cpu_map__has_any_cpu(event_cpus)) {
struct perf_cpu_map *online_cpus = perf_cpu_map__new_online_cpus();
/*
* In per-cpu case, do the validation for CPUs to work with.
* In per-thread case, the CPU map is empty. Since the traced
* program can run on any CPUs in this case, thus don't skip
* validation.
*/
if (!perf_cpu_map__has_any_cpu_or_is_empty(event_cpus) &&
!perf_cpu_map__has(event_cpus, cpu))
continue;
if (!perf_cpu_map__has(online_cpus, cpu))
continue;
err = cs_etm_validate_context_id(itr, evsel, i);
if (err)
goto out;
err = cs_etm_validate_timestamp(itr, evsel, i);
if (err)
goto out;
intersect_cpus = perf_cpu_map__intersect(event_cpus, online_cpus);
perf_cpu_map__put(online_cpus);
} else {
intersect_cpus = perf_cpu_map__new_online_cpus();
}
err = 0;
out:
perf_cpu_map__put(online_cpus);
perf_cpu_map__for_each_cpu_skip_any(cpu, idx, intersect_cpus) {
if (cs_etm_get_version(cs_etm_pmu, cpu) == CS_NOT_PRESENT) {
pr_err("%s: Not found on CPU %d. Check hardware and firmware support and that all Coresight drivers are loaded\n",
CORESIGHT_ETM_PMU_NAME, cpu.cpu);
return -EINVAL;
}
err = cs_etm_validate_context_id(cs_etm_pmu, evsel, cpu);
if (err)
break;
err = cs_etm_validate_timestamp(cs_etm_pmu, evsel, cpu);
if (err)
break;
}
perf_cpu_map__put(intersect_cpus);
return err;
}
@ -435,7 +440,7 @@ static int cs_etm_recording_options(struct auxtrace_record *itr,
* Also the case of per-cpu mmaps, need the contextID in order to be notified
* when a context switch happened.
*/
if (!perf_cpu_map__has_any_cpu_or_is_empty(cpus)) {
if (!perf_cpu_map__is_any_cpu_or_is_empty(cpus)) {
evsel__set_config_if_unset(cs_etm_pmu, cs_etm_evsel,
"timestamp", 1);
evsel__set_config_if_unset(cs_etm_pmu, cs_etm_evsel,
@ -461,10 +466,10 @@ static int cs_etm_recording_options(struct auxtrace_record *itr,
evsel->core.attr.sample_period = 1;
/* In per-cpu case, always need the time of mmap events etc */
if (!perf_cpu_map__has_any_cpu_or_is_empty(cpus))
if (!perf_cpu_map__is_any_cpu_or_is_empty(cpus))
evsel__set_sample_bit(evsel, TIME);
err = cs_etm_validate_config(itr, cs_etm_evsel);
err = cs_etm_validate_config(cs_etm_pmu, cs_etm_evsel);
out:
return err;
}
@ -530,48 +535,35 @@ static u64 cs_etmv4_get_config(struct auxtrace_record *itr)
}
static size_t
cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
struct evlist *evlist __maybe_unused)
cs_etm_info_priv_size(struct auxtrace_record *itr,
struct evlist *evlist)
{
int i;
int idx;
int etmv3 = 0, etmv4 = 0, ete = 0;
struct perf_cpu_map *event_cpus = evlist->core.user_requested_cpus;
struct perf_cpu_map *online_cpus = perf_cpu_map__new_online_cpus();
struct perf_cpu_map *intersect_cpus;
struct perf_cpu cpu;
struct perf_pmu *cs_etm_pmu = cs_etm_get_pmu(itr);
/* cpu map is not empty, we have specific CPUs to work with */
if (!perf_cpu_map__has_any_cpu_or_is_empty(event_cpus)) {
for (i = 0; i < cpu__max_cpu().cpu; i++) {
struct perf_cpu cpu = { .cpu = i, };
if (!perf_cpu_map__has_any_cpu(event_cpus)) {
/* cpu map is not "any" CPU , we have specific CPUs to work with */
struct perf_cpu_map *online_cpus = perf_cpu_map__new_online_cpus();
if (!perf_cpu_map__has(event_cpus, cpu) ||
!perf_cpu_map__has(online_cpus, cpu))
continue;
if (cs_etm_is_ete(itr, i))
ete++;
else if (cs_etm_is_etmv4(itr, i))
etmv4++;
else
etmv3++;
}
intersect_cpus = perf_cpu_map__intersect(event_cpus, online_cpus);
perf_cpu_map__put(online_cpus);
} else {
/* get configuration for all CPUs in the system */
for (i = 0; i < cpu__max_cpu().cpu; i++) {
struct perf_cpu cpu = { .cpu = i, };
if (!perf_cpu_map__has(online_cpus, cpu))
continue;
if (cs_etm_is_ete(itr, i))
ete++;
else if (cs_etm_is_etmv4(itr, i))
etmv4++;
else
etmv3++;
}
/* Event can be "any" CPU so count all online CPUs. */
intersect_cpus = perf_cpu_map__new_online_cpus();
}
/* Count number of each type of ETM. Don't count if that CPU has CS_NOT_PRESENT. */
perf_cpu_map__for_each_cpu_skip_any(cpu, idx, intersect_cpus) {
enum cs_etm_version v = cs_etm_get_version(cs_etm_pmu, cpu);
perf_cpu_map__put(online_cpus);
ete += v == CS_ETE;
etmv4 += v == CS_ETMV4;
etmv3 += v == CS_ETMV3;
}
perf_cpu_map__put(intersect_cpus);
return (CS_ETM_HEADER_SIZE +
(ete * CS_ETE_PRIV_SIZE) +
@ -579,66 +571,49 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
(etmv3 * CS_ETMV3_PRIV_SIZE));
}
static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu)
{
bool ret = false;
char path[PATH_MAX];
int scan;
unsigned int val;
struct cs_etm_recording *ptr =
container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
/* Take any of the RO files for ETMv4 and see if it present */
snprintf(path, PATH_MAX, "cpu%d/%s",
cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);
scan = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);
/* The file was read successfully, we have a winner */
if (scan == 1)
ret = true;
return ret;
}
static int cs_etm_get_ro(struct perf_pmu *pmu, int cpu, const char *path)
static int cs_etm_get_ro(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path, __u64 *val)
{
char pmu_path[PATH_MAX];
int scan;
unsigned int val = 0;
/* Get RO metadata from sysfs */
snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu, path);
snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu.cpu, path);
scan = perf_pmu__scan_file(pmu, pmu_path, "%x", &val);
if (scan != 1)
scan = perf_pmu__scan_file(pmu, pmu_path, "%llx", val);
if (scan != 1) {
pr_err("%s: error reading: %s\n", __func__, pmu_path);
return -EINVAL;
}
return val;
return 0;
}
static int cs_etm_get_ro_signed(struct perf_pmu *pmu, int cpu, const char *path)
static int cs_etm_get_ro_signed(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path,
__u64 *out_val)
{
char pmu_path[PATH_MAX];
int scan;
int val = 0;
/* Get RO metadata from sysfs */
snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu, path);
snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu.cpu, path);
scan = perf_pmu__scan_file(pmu, pmu_path, "%d", &val);
if (scan != 1)
if (scan != 1) {
pr_err("%s: error reading: %s\n", __func__, pmu_path);
return -EINVAL;
}
return val;
*out_val = (__u64) val;
return 0;
}
static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, int cpu, const char *path)
static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path)
{
char pmu_path[PATH_MAX];
/* Get RO metadata from sysfs */
snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu, path);
snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu.cpu, path);
return perf_pmu__file_exists(pmu, pmu_path);
}
@ -651,16 +626,14 @@ static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, int cpu, const char *pa
#define TRCDEVARCH_ARCHVER_MASK GENMASK(15, 12)
#define TRCDEVARCH_ARCHVER(x) (((x) & TRCDEVARCH_ARCHVER_MASK) >> TRCDEVARCH_ARCHVER_SHIFT)
static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu)
static bool cs_etm_is_ete(struct perf_pmu *cs_etm_pmu, struct perf_cpu cpu)
{
struct cs_etm_recording *ptr = container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
int trcdevarch;
__u64 trcdevarch;
if (!cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCDEVARCH]))
return false;
trcdevarch = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCDEVARCH]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCDEVARCH], &trcdevarch);
/*
* ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13.
* See ETM_DEVARCH_ETE_ARCH in coresight-etm4x.h
@ -668,7 +641,12 @@ static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu)
return TRCDEVARCH_ARCHVER(trcdevarch) == 5 && TRCDEVARCH_ARCHPART(trcdevarch) == 0xA13;
}
static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, int cpu)
static __u64 cs_etm_get_legacy_trace_id(struct perf_cpu cpu)
{
return CORESIGHT_LEGACY_CPU_TRACE_ID(cpu.cpu);
}
static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, struct perf_cpu cpu)
{
struct cs_etm_recording *ptr = container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
@ -676,33 +654,32 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr,
/* Get trace configuration register */
data[CS_ETMV4_TRCCONFIGR] = cs_etmv4_get_config(itr);
/* traceID set to legacy version, in case new perf running on older system */
data[CS_ETMV4_TRCTRACEIDR] =
CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG;
data[CS_ETMV4_TRCTRACEIDR] = cs_etm_get_legacy_trace_id(cpu) |
CORESIGHT_TRACE_ID_UNUSED_FLAG;
/* Get read-only information from sysFS */
data[CS_ETMV4_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);
data[CS_ETMV4_TRCIDR1] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_etmv4_ro[CS_ETMV4_TRCIDR1]);
data[CS_ETMV4_TRCIDR2] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_etmv4_ro[CS_ETMV4_TRCIDR2]);
data[CS_ETMV4_TRCIDR8] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_etmv4_ro[CS_ETMV4_TRCIDR8]);
data[CS_ETMV4_TRCAUTHSTATUS] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_etmv4_ro[CS_ETMV4_TRCAUTHSTATUS]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0],
&data[CS_ETMV4_TRCIDR0]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR1],
&data[CS_ETMV4_TRCIDR1]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR2],
&data[CS_ETMV4_TRCIDR2]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR8],
&data[CS_ETMV4_TRCIDR8]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCAUTHSTATUS],
&data[CS_ETMV4_TRCAUTHSTATUS]);
/* Kernels older than 5.19 may not expose ts_source */
if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TS_SOURCE]))
data[CS_ETMV4_TS_SOURCE] = (__u64) cs_etm_get_ro_signed(cs_etm_pmu, cpu,
metadata_etmv4_ro[CS_ETMV4_TS_SOURCE]);
else {
if (!cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TS_SOURCE]) ||
cs_etm_get_ro_signed(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TS_SOURCE],
&data[CS_ETMV4_TS_SOURCE])) {
pr_debug3("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n",
cpu);
cpu.cpu);
data[CS_ETMV4_TS_SOURCE] = (__u64) -1;
}
}
static void cs_etm_save_ete_header(__u64 data[], struct auxtrace_record *itr, int cpu)
static void cs_etm_save_ete_header(__u64 data[], struct auxtrace_record *itr, struct perf_cpu cpu)
{
struct cs_etm_recording *ptr = container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
@ -710,83 +687,85 @@ static void cs_etm_save_ete_header(__u64 data[], struct auxtrace_record *itr, in
/* Get trace configuration register */
data[CS_ETE_TRCCONFIGR] = cs_etmv4_get_config(itr);
/* traceID set to legacy version, in case new perf running on older system */
data[CS_ETE_TRCTRACEIDR] =
CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG;
data[CS_ETE_TRCTRACEIDR] = cs_etm_get_legacy_trace_id(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG;
/* Get read-only information from sysFS */
data[CS_ETE_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_ete_ro[CS_ETE_TRCIDR0]);
data[CS_ETE_TRCIDR1] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_ete_ro[CS_ETE_TRCIDR1]);
data[CS_ETE_TRCIDR2] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_ete_ro[CS_ETE_TRCIDR2]);
data[CS_ETE_TRCIDR8] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_ete_ro[CS_ETE_TRCIDR8]);
data[CS_ETE_TRCAUTHSTATUS] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_ete_ro[CS_ETE_TRCAUTHSTATUS]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCIDR0], &data[CS_ETE_TRCIDR0]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCIDR1], &data[CS_ETE_TRCIDR1]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCIDR2], &data[CS_ETE_TRCIDR2]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCIDR8], &data[CS_ETE_TRCIDR8]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCAUTHSTATUS],
&data[CS_ETE_TRCAUTHSTATUS]);
/* ETE uses the same registers as ETMv4 plus TRCDEVARCH */
data[CS_ETE_TRCDEVARCH] = cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_ete_ro[CS_ETE_TRCDEVARCH]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCDEVARCH],
&data[CS_ETE_TRCDEVARCH]);
/* Kernels older than 5.19 may not expose ts_source */
if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TS_SOURCE]))
data[CS_ETE_TS_SOURCE] = (__u64) cs_etm_get_ro_signed(cs_etm_pmu, cpu,
metadata_ete_ro[CS_ETE_TS_SOURCE]);
else {
if (!cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TS_SOURCE]) ||
cs_etm_get_ro_signed(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TS_SOURCE],
&data[CS_ETE_TS_SOURCE])) {
pr_debug3("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n",
cpu);
cpu.cpu);
data[CS_ETE_TS_SOURCE] = (__u64) -1;
}
}
static void cs_etm_get_metadata(int cpu, u32 *offset,
static void cs_etm_get_metadata(struct perf_cpu cpu, u32 *offset,
struct auxtrace_record *itr,
struct perf_record_auxtrace_info *info)
{
u32 increment, nr_trc_params;
u64 magic;
struct cs_etm_recording *ptr =
container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
struct perf_pmu *cs_etm_pmu = cs_etm_get_pmu(itr);
/* first see what kind of tracer this cpu is affined to */
if (cs_etm_is_ete(itr, cpu)) {
switch (cs_etm_get_version(cs_etm_pmu, cpu)) {
case CS_ETE:
magic = __perf_cs_ete_magic;
cs_etm_save_ete_header(&info->priv[*offset], itr, cpu);
/* How much space was used */
increment = CS_ETE_PRIV_MAX;
nr_trc_params = CS_ETE_PRIV_MAX - CS_ETM_COMMON_BLK_MAX_V1;
} else if (cs_etm_is_etmv4(itr, cpu)) {
break;
case CS_ETMV4:
magic = __perf_cs_etmv4_magic;
cs_etm_save_etmv4_header(&info->priv[*offset], itr, cpu);
/* How much space was used */
increment = CS_ETMV4_PRIV_MAX;
nr_trc_params = CS_ETMV4_PRIV_MAX - CS_ETMV4_TRCCONFIGR;
} else {
break;
case CS_ETMV3:
magic = __perf_cs_etmv3_magic;
/* Get configuration register */
info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr);
/* traceID set to legacy value in case new perf running on old system */
info->priv[*offset + CS_ETM_ETMTRACEIDR] =
CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG;
info->priv[*offset + CS_ETM_ETMTRACEIDR] = cs_etm_get_legacy_trace_id(cpu) |
CORESIGHT_TRACE_ID_UNUSED_FLAG;
/* Get read-only information from sysFS */
info->priv[*offset + CS_ETM_ETMCCER] =
cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_etmv3_ro[CS_ETM_ETMCCER]);
info->priv[*offset + CS_ETM_ETMIDR] =
cs_etm_get_ro(cs_etm_pmu, cpu,
metadata_etmv3_ro[CS_ETM_ETMIDR]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv3_ro[CS_ETM_ETMCCER],
&info->priv[*offset + CS_ETM_ETMCCER]);
cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv3_ro[CS_ETM_ETMIDR],
&info->priv[*offset + CS_ETM_ETMIDR]);
/* How much space was used */
increment = CS_ETM_PRIV_MAX;
nr_trc_params = CS_ETM_PRIV_MAX - CS_ETM_ETMCR;
break;
default:
case CS_NOT_PRESENT:
/* Unreachable, CPUs already validated in cs_etm_validate_config() */
assert(true);
return;
}
/* Build generic header portion */
info->priv[*offset + CS_ETM_MAGIC] = magic;
info->priv[*offset + CS_ETM_CPU] = cpu;
info->priv[*offset + CS_ETM_CPU] = cpu.cpu;
info->priv[*offset + CS_ETM_NR_TRC_PARAMS] = nr_trc_params;
/* Where the next CPU entry should start from */
*offset += increment;
@ -806,6 +785,7 @@ static int cs_etm_info_fill(struct auxtrace_record *itr,
struct cs_etm_recording *ptr =
container_of(itr, struct cs_etm_recording, itr);
struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
struct perf_cpu cpu;
if (priv_size != cs_etm_info_priv_size(itr, session->evlist))
return -EINVAL;
@ -813,16 +793,13 @@ static int cs_etm_info_fill(struct auxtrace_record *itr,
if (!session->evlist->core.nr_mmaps)
return -EINVAL;
/* If the cpu_map is empty all online CPUs are involved */
if (perf_cpu_map__has_any_cpu_or_is_empty(event_cpus)) {
/* If the cpu_map has the "any" CPU all online CPUs are involved */
if (perf_cpu_map__has_any_cpu(event_cpus)) {
cpu_map = online_cpus;
} else {
/* Make sure all specified CPUs are online */
for (i = 0; i < perf_cpu_map__nr(event_cpus); i++) {
struct perf_cpu cpu = { .cpu = i, };
if (perf_cpu_map__has(event_cpus, cpu) &&
!perf_cpu_map__has(online_cpus, cpu))
perf_cpu_map__for_each_cpu(cpu, i, event_cpus) {
if (!perf_cpu_map__has(online_cpus, cpu))
return -EINVAL;
}
@ -842,11 +819,9 @@ static int cs_etm_info_fill(struct auxtrace_record *itr,
offset = CS_ETM_SNAPSHOT + 1;
for (i = 0; i < cpu__max_cpu().cpu && offset < priv_size; i++) {
struct perf_cpu cpu = { .cpu = i, };
if (perf_cpu_map__has(cpu_map, cpu))
cs_etm_get_metadata(i, &offset, itr, info);
perf_cpu_map__for_each_cpu(cpu, i, cpu_map) {
assert(offset < priv_size);
cs_etm_get_metadata(cpu, &offset, itr, info);
}
perf_cpu_map__put(online_cpus);

4
tools/perf/arch/arm64/util/arm-spe.c
View File

@ -232,7 +232,7 @@ static int arm_spe_recording_options(struct auxtrace_record *itr,
* In the case of per-cpu mmaps, sample CPU for AUX event;
* also enable the timestamp tracing for samples correlation.
*/
if (!perf_cpu_map__has_any_cpu_or_is_empty(cpus)) {
if (!perf_cpu_map__is_any_cpu_or_is_empty(cpus)) {
evsel__set_sample_bit(arm_spe_evsel, CPU);
evsel__set_config_if_unset(arm_spe_pmu, arm_spe_evsel,
"ts_enable", 1);
@ -265,7 +265,7 @@ static int arm_spe_recording_options(struct auxtrace_record *itr,
tracking_evsel->core.attr.sample_period = 1;
/* In per-cpu case, always need the time of mmap events etc */
if (!perf_cpu_map__has_any_cpu_or_is_empty(cpus)) {
if (!perf_cpu_map__is_any_cpu_or_is_empty(cpus)) {
evsel__set_sample_bit(tracking_evsel, TIME);
evsel__set_sample_bit(tracking_evsel, CPU);

13
tools/perf/arch/arm64/util/header.c
View File

@ -4,8 +4,6 @@
#include <stdio.h>
#include <stdlib.h>
#include <perf/cpumap.h>
#include <util/cpumap.h>
#include <internal/cpumap.h>
#include <api/fs/fs.h>
#include <errno.h>
#include "debug.h"
@ -19,20 +17,18 @@
static int _get_cpuid(char *buf, size_t sz, struct perf_cpu_map *cpus)
{
const char *sysfs = sysfs__mountpoint();
int cpu;
int ret = EINVAL;
struct perf_cpu cpu;
int idx, ret = EINVAL;
if (!sysfs || sz < MIDR_SIZE)
return EINVAL;
cpus = perf_cpu_map__get(cpus);
for (cpu = 0; cpu < perf_cpu_map__nr(cpus); cpu++) {
perf_cpu_map__for_each_cpu(cpu, idx, cpus) {
char path[PATH_MAX];
FILE *file;
scnprintf(path, PATH_MAX, "%s/devices/system/cpu/cpu%d" MIDR,
sysfs, RC_CHK_ACCESS(cpus)->map[cpu].cpu);
sysfs, cpu.cpu);
file = fopen(path, "r");
if (!file) {
@ -51,7 +47,6 @@ static int _get_cpuid(char *buf, size_t sz, struct perf_cpu_map *cpus)
break;
}
perf_cpu_map__put(cpus);
return ret;
}

14
tools/perf/arch/x86/Build
View File

@ -1,2 +1,16 @@
perf-y += util/
perf-y += tests/
ifdef SHELLCHECK
SHELL_TESTS := entry/syscalls/syscalltbl.sh
TEST_LOGS := $(SHELL_TESTS:%=%.shellcheck_log)
else
SHELL_TESTS :=
TEST_LOGS :=
endif
$(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
perf-y += $(TEST_LOGS)

14
tools/perf/arch/x86/tests/Build
View File

@ -10,3 +10,17 @@ perf-$(CONFIG_AUXTRACE) += insn-x86.o
endif
perf-$(CONFIG_X86_64) += bp-modify.o
perf-y += amd-ibs-via-core-pmu.o
ifdef SHELLCHECK
SHELL_TESTS := gen-insn-x86-dat.sh
TEST_LOGS := $(SHELL_TESTS:%=%.shellcheck_log)
else
SHELL_TESTS :=
TEST_LOGS :=
endif
$(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
perf-y += $(TEST_LOGS)

2
tools/perf/arch/x86/tests/gen-insn-x86-dat.sh
View File

@ -11,7 +11,7 @@ if [ "$(uname -m)" != "x86_64" ]; then
exit 1
fi
cd $(dirname $0)
cd "$(dirname $0)"
trap 'echo "Might need a more recent version of binutils"' EXIT

4
tools/perf/arch/x86/util/intel-bts.c
View File

@ -143,7 +143,7 @@ static int intel_bts_recording_options(struct auxtrace_record *itr,
if (!opts->full_auxtrace)
return 0;
if (opts->full_auxtrace && !perf_cpu_map__has_any_cpu_or_is_empty(cpus)) {
if (opts->full_auxtrace && !perf_cpu_map__is_any_cpu_or_is_empty(cpus)) {
pr_err(INTEL_BTS_PMU_NAME " does not support per-cpu recording\n");
return -EINVAL;
}
@ -224,7 +224,7 @@ static int intel_bts_recording_options(struct auxtrace_record *itr,
* In the case of per-cpu mmaps, we need the CPU on the
* AUX event.
*/
if (!perf_cpu_map__has_any_cpu_or_is_empty(cpus))
if (!perf_cpu_map__is_any_cpu_or_is_empty(cpus))
evsel__set_sample_bit(intel_bts_evsel, CPU);
}

10
tools/perf/arch/x86/util/intel-pt.c
View File

@ -369,7 +369,7 @@ static int intel_pt_info_fill(struct auxtrace_record *itr,
ui__warning("Intel Processor Trace: TSC not available\n");
}
per_cpu_mmaps = !perf_cpu_map__has_any_cpu_or_is_empty(session->evlist->core.user_requested_cpus);
per_cpu_mmaps = !perf_cpu_map__is_any_cpu_or_is_empty(session->evlist->core.user_requested_cpus);
auxtrace_info->type = PERF_AUXTRACE_INTEL_PT;
auxtrace_info->priv[INTEL_PT_PMU_TYPE] = intel_pt_pmu->type;
@ -774,7 +774,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
* Per-cpu recording needs sched_switch events to distinguish different
* threads.
*/
if (have_timing_info && !perf_cpu_map__has_any_cpu_or_is_empty(cpus) &&
if (have_timing_info && !perf_cpu_map__is_any_cpu_or_is_empty(cpus) &&
!record_opts__no_switch_events(opts)) {
if (perf_can_record_switch_events()) {
bool cpu_wide = !target__none(&opts->target) &&
@ -832,7 +832,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
* In the case of per-cpu mmaps, we need the CPU on the
* AUX event.
*/
if (!perf_cpu_map__has_any_cpu_or_is_empty(cpus))
if (!perf_cpu_map__is_any_cpu_or_is_empty(cpus))
evsel__set_sample_bit(intel_pt_evsel, CPU);
}
@ -858,7 +858,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
tracking_evsel->immediate = true;
/* In per-cpu case, always need the time of mmap events etc */
if (!perf_cpu_map__has_any_cpu_or_is_empty(cpus)) {
if (!perf_cpu_map__is_any_cpu_or_is_empty(cpus)) {
evsel__set_sample_bit(tracking_evsel, TIME);
/* And the CPU for switch events */
evsel__set_sample_bit(tracking_evsel, CPU);
@ -870,7 +870,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
* Warn the user when we do not have enough information to decode i.e.
* per-cpu with no sched_switch (except workload-only).
*/
if (!ptr->have_sched_switch && !perf_cpu_map__has_any_cpu_or_is_empty(cpus) &&
if (!ptr->have_sched_switch && !perf_cpu_map__is_any_cpu_or_is_empty(cpus) &&
!target__none(&opts->target) &&
!intel_pt_evsel->core.attr.exclude_user)
ui__warning("Intel Processor Trace decoding will not be possible except for kernel tracing!\n");

2
tools/perf/bench/bench.h
View File

@ -46,6 +46,8 @@ int bench_breakpoint_enable(int argc, const char **argv);
int bench_uprobe_baseline(int argc, const char **argv);
int bench_uprobe_empty(int argc, const char **argv);
int bench_uprobe_trace_printk(int argc, const char **argv);
int bench_uprobe_empty_ret(int argc, const char **argv);
int bench_uprobe_trace_printk_ret(int argc, const char **argv);
int bench_pmu_scan(int argc, const char **argv);
#define BENCH_FORMAT_DEFAULT_STR "default"

2
tools/perf/bench/inject-buildid.c
View File

@ -362,7 +362,7 @@ static int inject_build_id(struct bench_data *data, u64 *max_rss)
return -1;
for (i = 0; i < nr_mmaps; i++) {
int idx = rand() % (nr_dsos - 1);
int idx = rand() % nr_dsos;
struct bench_dso *dso = &dsos[idx];
u64 timestamp = rand() % 1000000;

22
tools/perf/bench/uprobe.c
View File

@ -26,9 +26,11 @@
static int loops = LOOPS_DEFAULT;
enum bench_uprobe {
BENCH_UPROBE__BASELINE,
BENCH_UPROBE__EMPTY,
BENCH_UPROBE__TRACE_PRINTK,
BENCH_UPROBE__BASELINE,
BENCH_UPROBE__EMPTY,
BENCH_UPROBE__TRACE_PRINTK,
BENCH_UPROBE__EMPTY_RET,
BENCH_UPROBE__TRACE_PRINTK_RET,
};
static const struct option options[] = {
@ -47,7 +49,7 @@ static const char * const bench_uprobe_usage[] = {
#define bench_uprobe__attach_uprobe(prog) \
skel->links.prog = bpf_program__attach_uprobe_opts(/*prog=*/skel->progs.prog, \
/*pid=*/-1, \
/*binary_path=*/"/lib64/libc.so.6", \
/*binary_path=*/"libc.so.6", \
/*func_offset=*/0, \
/*opts=*/&uprobe_opts); \
if (!skel->links.prog) { \
@ -81,6 +83,8 @@ static int bench_uprobe__setup_bpf_skel(enum bench_uprobe bench)
case BENCH_UPROBE__BASELINE: break;
case BENCH_UPROBE__EMPTY: bench_uprobe__attach_uprobe(empty); break;
case BENCH_UPROBE__TRACE_PRINTK: bench_uprobe__attach_uprobe(trace_printk); break;
case BENCH_UPROBE__EMPTY_RET: bench_uprobe__attach_uprobe(empty_ret); break;
case BENCH_UPROBE__TRACE_PRINTK_RET: bench_uprobe__attach_uprobe(trace_printk_ret); break;
default:
fprintf(stderr, "Invalid bench: %d\n", bench);
goto cleanup;
@ -197,3 +201,13 @@ int bench_uprobe_trace_printk(int argc, const char **argv)
{
return bench_uprobe(argc, argv, BENCH_UPROBE__TRACE_PRINTK);
}
int bench_uprobe_empty_ret(int argc, const char **argv)
{
return bench_uprobe(argc, argv, BENCH_UPROBE__EMPTY_RET);
}
int bench_uprobe_trace_printk_ret(int argc, const char **argv)
{
return bench_uprobe(argc, argv, BENCH_UPROBE__TRACE_PRINTK_RET);
}

128
tools/perf/builtin-annotate.c
View File

@ -37,11 +37,13 @@
#include "util/map_symbol.h"
#include "util/branch.h"
#include "util/util.h"
#include "ui/progress.h"
#include <dlfcn.h>
#include <errno.h>
#include <linux/bitmap.h>
#include <linux/err.h>
#include <inttypes.h>
struct perf_annotate {
struct perf_tool tool;
@ -217,7 +219,7 @@ static int process_branch_callback(struct evsel *evsel,
}
if (a.map != NULL)
map__dso(a.map)->hit = 1;
dso__set_hit(map__dso(a.map));
hist__account_cycles(sample->branch_stack, al, sample, false, NULL);
@ -252,7 +254,7 @@ static int evsel__add_sample(struct evsel *evsel, struct perf_sample *sample,
if (al->sym != NULL) {
struct dso *dso = map__dso(al->map);
rb_erase_cached(&al->sym->rb_node, &dso->symbols);
rb_erase_cached(&al->sym->rb_node, dso__symbols(dso));
symbol__delete(al->sym);
dso__reset_find_symbol_cache(dso);
}
@ -327,77 +329,6 @@ static int hist_entry__tty_annotate(struct hist_entry *he,
return symbol__tty_annotate2(&he->ms, evsel);
}
static void print_annotated_data_header(struct hist_entry *he, struct evsel *evsel)
{
struct dso *dso = map__dso(he->ms.map);
int nr_members = 1;
int nr_samples = he->stat.nr_events;
if (evsel__is_group_event(evsel)) {
struct hist_entry *pair;
list_for_each_entry(pair, &he->pairs.head, pairs.node)
nr_samples += pair->stat.nr_events;
}
printf("Annotate type: '%s' in %s (%d samples):\n",
he->mem_type->self.type_name, dso->name, nr_samples);
if (evsel__is_group_event(evsel)) {
struct evsel *pos;
int i = 0;
for_each_group_evsel(pos, evsel)
printf(" event[%d] = %s\n", i++, pos->name);
nr_members = evsel->core.nr_members;
}
printf("============================================================================\n");
printf("%*s %10s %10s %s\n", 11 * nr_members, "samples", "offset", "size", "field");
}
static void print_annotated_data_type(struct annotated_data_type *mem_type,
struct annotated_member *member,
struct evsel *evsel, int indent)
{
struct annotated_member *child;
struct type_hist *h = mem_type->histograms[evsel->core.idx];
int i, nr_events = 1, samples = 0;
for (i = 0; i < member->size; i++)
samples += h->addr[member->offset + i].nr_samples;
printf(" %10d", samples);
if (evsel__is_group_event(evsel)) {
struct evsel *pos;
for_each_group_member(pos, evsel) {
h = mem_type->histograms[pos->core.idx];
samples = 0;
for (i = 0; i < member->size; i++)
samples += h->addr[member->offset + i].nr_samples;
printf(" %10d", samples);
}
nr_events = evsel->core.nr_members;
}
printf(" %10d %10d %*s%s\t%s",
member->offset, member->size, indent, "", member->type_name,
member->var_name ?: "");
if (!list_empty(&member->children))
printf(" {\n");
list_for_each_entry(child, &member->children, node)
print_annotated_data_type(mem_type, child, evsel, indent + 4);
if (!list_empty(&member->children))
printf("%*s}", 11 * nr_events + 24 + indent, "");
printf(";\n");
}
static void print_annotate_data_stat(struct annotated_data_stat *s)
{
#define PRINT_STAT(fld) if (s->fld) printf("%10d : %s\n", s->fld, #fld)
@ -430,6 +361,7 @@ static void print_annotate_data_stat(struct annotated_data_stat *s)
PRINT_STAT(no_typeinfo);
PRINT_STAT(invalid_size);
PRINT_STAT(bad_offset);
PRINT_STAT(insn_track);
printf("\n");
#undef PRINT_STAT
@ -487,7 +419,7 @@ static void hists__find_annotations(struct hists *hists,
struct hist_entry *he = rb_entry(nd, struct hist_entry, rb_node);
struct annotation *notes;
if (he->ms.sym == NULL || map__dso(he->ms.map)->annotate_warned)
if (he->ms.sym == NULL || dso__annotate_warned(map__dso(he->ms.map)))
goto find_next;
if (ann->sym_hist_filter &&
@ -537,10 +469,32 @@ find_next:
goto find_next;
}
print_annotated_data_header(he, evsel);
print_annotated_data_type(he->mem_type, &he->mem_type->self, evsel, 0);
printf("\n");
goto find_next;
if (use_browser == 1)
key = hist_entry__annotate_data_tui(he, evsel, NULL);
else
key = hist_entry__annotate_data_tty(he, evsel);
switch (key) {
case -1:
if (!ann->skip_missing)
return;
/* fall through */
case K_RIGHT:
case '>':
next = rb_next(nd);
break;
case K_LEFT:
case '<':
next = rb_prev(nd);
break;
default:
return;
}
if (use_browser == 0 || next != NULL)
nd = next;
continue;
}
if (use_browser == 2) {
@ -632,13 +586,23 @@ static int __cmd_annotate(struct perf_annotate *ann)
evlist__for_each_entry(session->evlist, pos) {
struct hists *hists = evsel__hists(pos);
u32 nr_samples = hists->stats.nr_samples;
struct ui_progress prog;
if (nr_samples > 0) {
total_nr_samples += nr_samples;
hists__collapse_resort(hists, NULL);
ui_progress__init(&prog, nr_samples,
"Merging related events...");
hists__collapse_resort(hists, &prog);
ui_progress__finish();
/* Don't sort callchain */
evsel__reset_sample_bit(pos, CALLCHAIN);
evsel__output_resort(pos, NULL);
ui_progress__init(&prog, nr_samples,
"Sorting events for output...");
evsel__output_resort(pos, &prog);
ui_progress__finish();
/*
* An event group needs to display other events too.
@ -809,8 +773,6 @@ int cmd_annotate(int argc, const char **argv)
"Enable symbol demangling"),
OPT_BOOLEAN(0, "demangle-kernel", &symbol_conf.demangle_kernel,
"Enable kernel symbol demangling"),
OPT_BOOLEAN(0, "group", &symbol_conf.event_group,
"Show event group information together"),
OPT_BOOLEAN(0, "show-total-period", &symbol_conf.show_total_period,
"Show a column with the sum of periods"),
OPT_BOOLEAN('n', "show-nr-samples", &symbol_conf.show_nr_samples,
@ -935,9 +897,7 @@ int cmd_annotate(int argc, const char **argv)
use_browser = 2;
#endif
/* FIXME: only support stdio for now */
if (annotate.data_type) {
use_browser = 0;
annotate_opts.annotate_src = false;
symbol_conf.annotate_data_member = true;
symbol_conf.annotate_data_sample = true;

2
tools/perf/builtin-bench.c
View File

@ -109,6 +109,8 @@ static struct bench uprobe_benchmarks[] = {
{ "baseline", "Baseline libc usleep(1000) call", bench_uprobe_baseline, },
{ "empty", "Attach empty BPF prog to uprobe on usleep, system wide", bench_uprobe_empty, },
{ "trace_printk", "Attach trace_printk BPF prog to uprobe on usleep syswide", bench_uprobe_trace_printk, },
{ "empty_ret", "Attach empty BPF prog to uretprobe on usleep, system wide", bench_uprobe_empty_ret, },
{ "trace_printk_ret", "Attach trace_printk BPF prog to uretprobe on usleep syswide", bench_uprobe_trace_printk_ret,},
{ NULL, NULL, NULL },
};

2
tools/perf/builtin-buildid-cache.c
View File

@ -286,7 +286,7 @@ static bool dso__missing_buildid_cache(struct dso *dso, int parm __maybe_unused)
pr_warning("Problems with %s file, consider removing it from the cache\n",
filename);
} else if (memcmp(dso->bid.data, bid.data, bid.size)) {
} else if (memcmp(dso__bid(dso)->data, bid.data, bid.size)) {
pr_warning("Problems with %s file, consider removing it from the cache\n",
filename);
}

18
tools/perf/builtin-buildid-list.c
View File

@ -26,16 +26,18 @@ static int buildid__map_cb(struct map *map, void *arg __maybe_unused)
{
const struct dso *dso = map__dso(map);
char bid_buf[SBUILD_ID_SIZE];
const char *dso_long_name = dso__long_name(dso);
const char *dso_short_name = dso__short_name(dso);
memset(bid_buf, 0, sizeof(bid_buf));
if (dso->has_build_id)
build_id__sprintf(&dso->bid, bid_buf);
if (dso__has_build_id(dso))
build_id__sprintf(dso__bid_const(dso), bid_buf);
printf("%s %16" PRIx64 " %16" PRIx64, bid_buf, map__start(map), map__end(map));
if (dso->long_name != NULL) {
printf(" %s", dso->long_name);
} else if (dso->short_name != NULL) {
printf(" %s", dso->short_name);
}
if (dso_long_name != NULL)
printf(" %s", dso_long_name);
else if (dso_short_name != NULL)
printf(" %s", dso_short_name);
printf("\n");
return 0;
@ -76,7 +78,7 @@ static int filename__fprintf_build_id(const char *name, FILE *fp)
static bool dso__skip_buildid(struct dso *dso, int with_hits)
{
return with_hits && !dso->hit;
return with_hits && !dso__hit(dso);
}
static int perf_session__list_build_ids(bool force, bool with_hits)

21
tools/perf/builtin-c2c.c
View File

@ -38,6 +38,7 @@
#include "ui/browsers/hists.h"
#include "thread.h"
#include "mem2node.h"
#include "mem-info.h"
#include "symbol.h"
#include "ui/ui.h"
#include "ui/progress.h"
@ -529,7 +530,7 @@ static int dcacheline_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
char buf[20];
if (he->mem_info)
addr = cl_address(he->mem_info->daddr.addr, chk_double_cl);
addr = cl_address(mem_info__daddr(he->mem_info)->addr, chk_double_cl);
return scnprintf(hpp->buf, hpp->size, "%*s", width, HEX_STR(buf, addr));
}
@ -567,7 +568,7 @@ static int offset_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
char buf[20];
if (he->mem_info)
addr = cl_offset(he->mem_info->daddr.al_addr, chk_double_cl);
addr = cl_offset(mem_info__daddr(he->mem_info)->al_addr, chk_double_cl);
return scnprintf(hpp->buf, hpp->size, "%*s", width, HEX_STR(buf, addr));
}
@ -579,10 +580,10 @@ offset_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
uint64_t l = 0, r = 0;
if (left->mem_info)
l = cl_offset(left->mem_info->daddr.addr, chk_double_cl);
l = cl_offset(mem_info__daddr(left->mem_info)->addr, chk_double_cl);
if (right->mem_info)
r = cl_offset(right->mem_info->daddr.addr, chk_double_cl);
r = cl_offset(mem_info__daddr(right->mem_info)->addr, chk_double_cl);
return (int64_t)(r - l);
}
@ -596,7 +597,7 @@ iaddr_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
char buf[20];
if (he->mem_info)
addr = he->mem_info->iaddr.addr;
addr = mem_info__iaddr(he->mem_info)->addr;
return scnprintf(hpp->buf, hpp->size, "%*s", width, HEX_STR(buf, addr));
}
@ -2050,7 +2051,7 @@ static int hpp_list__parse(struct perf_hpp_list *hpp_list,
perf_hpp__setup_output_field(hpp_list);
/*
* We dont need other sorting keys other than those
* We don't need other sorting keys other than those
* we already specified. It also really slows down
* the processing a lot with big number of output
* fields, so switching this off for c2c.
@ -2319,11 +2320,7 @@ static int setup_nodes(struct perf_session *session)
nodes[node] = set;
/* empty node, skip */
if (perf_cpu_map__has_any_cpu_or_is_empty(map))
continue;
perf_cpu_map__for_each_cpu(cpu, idx, map) {
perf_cpu_map__for_each_cpu_skip_any(cpu, idx, map) {
__set_bit(cpu.cpu, set);
if (WARN_ONCE(cpu2node[cpu.cpu] != -1, "node/cpu topology bug"))
@ -2596,7 +2593,7 @@ perf_c2c_cacheline_browser__title(struct hist_browser *browser,
he = cl_browser->he;
if (he->mem_info)
addr = cl_address(he->mem_info->daddr.addr, chk_double_cl);
addr = cl_address(mem_info__daddr(he->mem_info)->addr, chk_double_cl);
scnprintf(bf, size, "Cacheline 0x%lx", addr);
return 0;

4
tools/perf/builtin-daemon.c
View File

@ -523,7 +523,7 @@ static int daemon_session__control(struct daemon_session *session,
session->base, SESSION_CONTROL);
control = open(control_path, O_WRONLY|O_NONBLOCK);
if (!control)
if (control < 0)
return -1;
if (do_ack) {
@ -532,7 +532,7 @@ static int daemon_session__control(struct daemon_session *session,
session->base, SESSION_ACK);
ack = open(ack_path, O_RDONLY, O_NONBLOCK);
if (!ack) {
if (ack < 0) {
close(control);
return -1;
}

96
tools/perf/builtin-inject.c
View File

@ -445,10 +445,9 @@ static struct dso *findnew_dso(int pid, int tid, const char *filename,
}
if (dso) {
mutex_lock(&dso->lock);
nsinfo__put(dso->nsinfo);
dso->nsinfo = nsi;
mutex_unlock(&dso->lock);
mutex_lock(dso__lock(dso));
dso__set_nsinfo(dso, nsi);
mutex_unlock(dso__lock(dso));
} else
nsinfo__put(nsi);
@ -466,8 +465,8 @@ static int perf_event__repipe_buildid_mmap(struct perf_tool *tool,
dso = findnew_dso(event->mmap.pid, event->mmap.tid,
event->mmap.filename, NULL, machine);
if (dso && !dso->hit) {
dso->hit = 1;
if (dso && !dso__hit(dso)) {
dso__set_hit(dso);
dso__inject_build_id(dso, tool, machine, sample->cpumode, 0);
}
dso__put(dso);
@ -492,7 +491,7 @@ static int perf_event__repipe_mmap2(struct perf_tool *tool,
event->mmap2.filename, NULL, machine);
if (dso) {
/* mark it not to inject build-id */
dso->hit = 1;
dso__set_hit(dso);
}
dso__put(dso);
}
@ -544,7 +543,7 @@ static int perf_event__repipe_buildid_mmap2(struct perf_tool *tool,
event->mmap2.filename, NULL, machine);
if (dso) {
/* mark it not to inject build-id */
dso->hit = 1;
dso__set_hit(dso);
}
dso__put(dso);
perf_event__repipe(tool, event, sample, machine);
@ -554,8 +553,8 @@ static int perf_event__repipe_buildid_mmap2(struct perf_tool *tool,
dso = findnew_dso(event->mmap2.pid, event->mmap2.tid,
event->mmap2.filename, &dso_id, machine);
if (dso && !dso->hit) {
dso->hit = 1;
if (dso && !dso__hit(dso)) {
dso__set_hit(dso);
dso__inject_build_id(dso, tool, machine, sample->cpumode,
event->mmap2.flags);
}
@ -631,24 +630,24 @@ static int dso__read_build_id(struct dso *dso)
{
struct nscookie nsc;
if (dso->has_build_id)
if (dso__has_build_id(dso))
return 0;
mutex_lock(&dso->lock);
nsinfo__mountns_enter(dso->nsinfo, &nsc);
if (filename__read_build_id(dso->long_name, &dso->bid) > 0)
dso->has_build_id = true;
else if (dso->nsinfo) {
char *new_name = dso__filename_with_chroot(dso, dso->long_name);
mutex_lock(dso__lock(dso));
nsinfo__mountns_enter(dso__nsinfo(dso), &nsc);
if (filename__read_build_id(dso__long_name(dso), dso__bid(dso)) > 0)
dso__set_has_build_id(dso);
else if (dso__nsinfo(dso)) {
char *new_name = dso__filename_with_chroot(dso, dso__long_name(dso));
if (new_name && filename__read_build_id(new_name, &dso->bid) > 0)
dso->has_build_id = true;
if (new_name && filename__read_build_id(new_name, dso__bid(dso)) > 0)
dso__set_has_build_id(dso);
free(new_name);
}
nsinfo__mountns_exit(&nsc);
mutex_unlock(&dso->lock);
mutex_unlock(dso__lock(dso));
return dso->has_build_id ? 0 : -1;
return dso__has_build_id(dso) ? 0 : -1;
}
static struct strlist *perf_inject__parse_known_build_ids(
@ -700,14 +699,14 @@ static bool perf_inject__lookup_known_build_id(struct perf_inject *inject,
dso_name = strchr(build_id, ' ');
bid_len = dso_name - pos->s;
dso_name = skip_spaces(dso_name);
if (strcmp(dso->long_name, dso_name))
if (strcmp(dso__long_name(dso), dso_name))
continue;
for (int ix = 0; 2 * ix + 1 < bid_len; ++ix) {
dso->bid.data[ix] = (hex(build_id[2 * ix]) << 4 |
hex(build_id[2 * ix + 1]));
dso__bid(dso)->data[ix] = (hex(build_id[2 * ix]) << 4 |
hex(build_id[2 * ix + 1]));
}
dso->bid.size = bid_len / 2;
dso->has_build_id = 1;
dso__bid(dso)->size = bid_len / 2;
dso__set_has_build_id(dso);
return true;
}
return false;
@ -720,9 +719,9 @@ static int dso__inject_build_id(struct dso *dso, struct perf_tool *tool,
tool);
int err;
if (is_anon_memory(dso->long_name) || flags & MAP_HUGETLB)
if (is_anon_memory(dso__long_name(dso)) || flags & MAP_HUGETLB)
return 0;
if (is_no_dso_memory(dso->long_name))
if (is_no_dso_memory(dso__long_name(dso)))
return 0;
if (inject->known_build_ids != NULL &&
@ -730,14 +729,14 @@ static int dso__inject_build_id(struct dso *dso, struct perf_tool *tool,
return 1;
if (dso__read_build_id(dso) < 0) {
pr_debug("no build_id found for %s\n", dso->long_name);
pr_debug("no build_id found for %s\n", dso__long_name(dso));
return -1;
}
err = perf_event__synthesize_build_id(tool, dso, cpumode,
perf_event__repipe, machine);
if (err) {
pr_err("Can't synthesize build_id event for %s\n", dso->long_name);
pr_err("Can't synthesize build_id event for %s\n", dso__long_name(dso));
return -1;
}
@ -763,8 +762,8 @@ int perf_event__inject_buildid(struct perf_tool *tool, union perf_event *event,
if (thread__find_map(thread, sample->cpumode, sample->ip, &al)) {
struct dso *dso = map__dso(al.map);
if (!dso->hit) {
dso->hit = 1;
if (!dso__hit(dso)) {
dso__set_hit(dso);
dso__inject_build_id(dso, tool, machine,
sample->cpumode, map__flags(al.map));
}
@ -1146,8 +1145,8 @@ static bool dso__is_in_kernel_space(struct dso *dso)
return false;
return dso__is_kcore(dso) ||
dso->kernel ||
is_kernel_module(dso->long_name, PERF_RECORD_MISC_CPUMODE_UNKNOWN);
dso__kernel(dso) ||
is_kernel_module(dso__long_name(dso), PERF_RECORD_MISC_CPUMODE_UNKNOWN);
}
static u64 evlist__first_id(struct evlist *evlist)
@ -1181,29 +1180,34 @@ static int synthesize_build_id(struct perf_inject *inject, struct dso *dso, pid_
if (!machine)
return -ENOMEM;
dso->hit = 1;
dso__set_hit(dso);
return perf_event__synthesize_build_id(&inject->tool, dso, cpumode,
process_build_id, machine);
}
static int guest_session__add_build_ids_cb(struct dso *dso, void *data)
{
struct guest_session *gs = data;
struct perf_inject *inject = container_of(gs, struct perf_inject, guest_session);
if (!dso__has_build_id(dso))
return 0;
return synthesize_build_id(inject, dso, gs->machine_pid);
}
static int guest_session__add_build_ids(struct guest_session *gs)
{
struct perf_inject *inject = container_of(gs, struct perf_inject, guest_session);
struct machine *machine = &gs->session->machines.host;
struct dso *dso;
int ret;
/* Build IDs will be put in the Build ID feature section */
perf_header__set_feat(&inject->session->header, HEADER_BUILD_ID);
dsos__for_each_with_build_id(dso, &machine->dsos.head) {
ret = synthesize_build_id(inject, dso, gs->machine_pid);
if (ret)
return ret;
}
return 0;
return dsos__for_each_dso(&gs->session->machines.host.dsos,
guest_session__add_build_ids_cb,
gs);
}
static int guest_session__ksymbol_event(struct perf_tool *tool,
@ -2122,7 +2126,7 @@ static int __cmd_inject(struct perf_inject *inject)
*/
if (perf_header__has_feat(&session->header, HEADER_BUILD_ID) &&
inject->have_auxtrace && !inject->itrace_synth_opts.set)
dsos__hit_all(session);
perf_session__dsos_hit_all(session);
/*
* The AUX areas have been removed and replaced with
* synthesized hardware events, so clear the feature flag.

2
tools/perf/builtin-kallsyms.c
View File

@ -38,7 +38,7 @@ static int __cmd_kallsyms(int argc, const char **argv)
dso = map__dso(map);
printf("%s: %s %s %#" PRIx64 "-%#" PRIx64 " (%#" PRIx64 "-%#" PRIx64")\n",
symbol->name, dso->short_name, dso->long_name,
symbol->name, dso__short_name(dso), dso__long_name(dso),
map__unmap_ip(map, symbol->start), map__unmap_ip(map, symbol->end),
symbol->start, symbol->end);
}

2
tools/perf/builtin-kmem.c
View File

@ -1408,7 +1408,7 @@ static int __cmd_kmem(struct perf_session *session)
}
evlist__for_each_entry(session->evlist, evsel) {
if (!strcmp(evsel__name(evsel), "kmem:mm_page_alloc") &&
if (evsel__name_is(evsel, "kmem:mm_page_alloc") &&
evsel__field(evsel, "pfn")) {
use_pfn = true;
break;

2
tools/perf/builtin-kwork.c
View File

@ -2230,7 +2230,7 @@ static int perf_kwork__top(struct perf_kwork *kwork)
perf_kwork__top_report(kwork);
out:
free(kwork->top_stat.cpus_runtime);
zfree(&kwork->top_stat.cpus_runtime);
return ret;
}

24
tools/perf/builtin-list.c
View File

@ -22,6 +22,7 @@
#include <subcmd/pager.h>
#include <subcmd/parse-options.h>
#include <linux/zalloc.h>
#include <ctype.h>
#include <stdarg.h>
#include <stdio.h>
@ -76,26 +77,38 @@ static void default_print_start(void *ps)
static void default_print_end(void *print_state __maybe_unused) {}
static const char *skip_spaces_or_commas(const char *str)
{
while (isspace(*str) || *str == ',')
++str;
return str;
}
static void wordwrap(FILE *fp, const char *s, int start, int max, int corr)
{
int column = start;
int n;
bool saw_newline = false;
bool comma = false;
while (*s) {
int wlen = strcspn(s, " \t\n");
int wlen = strcspn(s, " ,\t\n");
const char *sep = comma ? "," : " ";
if ((column + wlen >= max && column > start) || saw_newline) {
fprintf(fp, "\n%*s", start, "");
fprintf(fp, comma ? ",\n%*s" : "\n%*s", start, "");
column = start + corr;
}
n = fprintf(fp, "%s%.*s", column > start ? " " : "", wlen, s);
if (column <= start)
sep = "";
n = fprintf(fp, "%s%.*s", sep, wlen, s);
if (n <= 0)
break;
saw_newline = s[wlen] == '\n';
s += wlen;
comma = s[0] == ',';
column += n;
s = skip_spaces(s);
s = skip_spaces_or_commas(s);
}
}
@ -313,6 +326,9 @@ static void fix_escape_fprintf(FILE *fp, struct strbuf *buf, const char *fmt, ..
case '\n':
strbuf_addstr(buf, "\\n");
break;
case '\r':
strbuf_addstr(buf, "\\r");
break;
case '\\':
fallthrough;
case '\"':

18
tools/perf/builtin-lock.c
View File

@ -2275,23 +2275,13 @@ setup_args:
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(record_args); i++)
rec_argv[i] = strdup(record_args[i]);
rec_argv[i] = record_args[i];
for (j = 0; j < nr_tracepoints; j++) {
const char *ev_name;
if (has_lock_stat)
ev_name = strdup(lock_tracepoints[j].name);
else
ev_name = strdup(contention_tracepoints[j].name);
if (!ev_name) {
free(rec_argv);
return -ENOMEM;
}
rec_argv[i++] = "-e";
rec_argv[i++] = ev_name;
rec_argv[i++] = has_lock_stat
? lock_tracepoints[j].name
: contention_tracepoints[j].name;
}
for (j = 0; j < nr_callgraph_args; j++, i++)

4
tools/perf/builtin-mem.c
View File

@ -213,7 +213,7 @@ dump_raw_samples(struct perf_tool *tool,
if (al.map != NULL) {
dso = map__dso(al.map);
if (dso)
dso->hit = 1;
dso__set_hit(dso);
}
field_sep = symbol_conf.field_sep;
@ -255,7 +255,7 @@ dump_raw_samples(struct perf_tool *tool,
symbol_conf.field_sep,
sample->data_src,
symbol_conf.field_sep,
dso ? dso->long_name : "???",
dso ? dso__long_name(dso) : "???",
al.sym ? al.sym->name : "???");
out_put:
addr_location__exit(&al);

2
tools/perf/builtin-probe.c
View File

@ -325,7 +325,7 @@ static void cleanup_params(void)
for (i = 0; i < params->nevents; i++)
clear_perf_probe_event(params->events + i);
line_range__clear(&params->line_range);
free(params->target);
zfree(&params->target);
strfilter__delete(params->filter);
nsinfo__put(params->nsi);
zfree(&params);

14
tools/perf/builtin-record.c
View File

@ -332,7 +332,7 @@ static int record__aio_complete(struct mmap *md, struct aiocb *cblock)
} else {
/*
* aio write request may require restart with the
* reminder if the kernel didn't write whole
* remainder if the kernel didn't write whole
* chunk at once.
*/
rem_off = cblock->aio_offset + written;
@ -400,7 +400,7 @@ static int record__aio_pushfn(struct mmap *map, void *to, void *buf, size_t size
*
* Coping can be done in two steps in case the chunk of profiling data
* crosses the upper bound of the kernel buffer. In this case we first move
* part of data from map->start till the upper bound and then the reminder
* part of data from map->start till the upper bound and then the remainder
* from the beginning of the kernel buffer till the end of the data chunk.
*/
@ -1355,8 +1355,6 @@ static int record__open(struct record *rec)
struct record_opts *opts = &rec->opts;
int rc = 0;
evlist__config(evlist, opts, &callchain_param);
evlist__for_each_entry(evlist, pos) {
try_again:
if (evsel__open(pos, pos->core.cpus, pos->core.threads) < 0) {
@ -1790,7 +1788,7 @@ record__finish_output(struct record *rec)
process_buildids(rec);
if (rec->buildid_all)
dsos__hit_all(rec->session);
perf_session__dsos_hit_all(rec->session);
}
perf_session__write_header(rec->session, rec->evlist, fd, true);
@ -2483,6 +2481,8 @@ static int __cmd_record(struct record *rec, int argc, const char **argv)
evlist__uniquify_name(rec->evlist);
evlist__config(rec->evlist, opts, &callchain_param);
/* Debug message used by test scripts */
pr_debug3("perf record opening and mmapping events\n");
if (record__open(rec) != 0) {
@ -2881,10 +2881,10 @@ out_delete_session:
}
#endif
zstd_fini(&session->zstd_data);
perf_session__delete(session);
if (!opts->no_bpf_event)
evlist__stop_sb_thread(rec->sb_evlist);
perf_session__delete(session);
return status;
}

18
tools/perf/builtin-report.c
View File

@ -31,6 +31,7 @@
#include "util/evsel.h"
#include "util/evswitch.h"
#include "util/header.h"
#include "util/mem-info.h"
#include "util/session.h"
#include "util/srcline.h"
#include "util/tool.h"
@ -172,7 +173,7 @@ static int hist_iter__report_callback(struct hist_entry_iter *iter,
struct mem_info *mi;
struct branch_info *bi;
if (!ui__has_annotation() && !rep->symbol_ipc && !rep->data_type)
if (!ui__has_annotation() && !rep->symbol_ipc)
return 0;
if (sort__mode == SORT_MODE__BRANCH) {
@ -185,7 +186,7 @@ static int hist_iter__report_callback(struct hist_entry_iter *iter,
} else if (rep->mem_mode) {
mi = he->mem_info;
err = addr_map_symbol__inc_samples(&mi->daddr, sample, evsel);
err = addr_map_symbol__inc_samples(mem_info__daddr(mi), sample, evsel);
if (err)
goto out;
@ -322,7 +323,7 @@ static int process_sample_event(struct perf_tool *tool,
}
if (al.map != NULL)
map__dso(al.map)->hit = 1;
dso__set_hit(map__dso(al.map));
if (ui__has_annotation() || rep->symbol_ipc || rep->total_cycles_mode) {
hist__account_cycles(sample->branch_stack, &al, sample,
@ -428,7 +429,7 @@ static int report__setup_sample_type(struct report *rep)
* compatibility, set the bit if it's an old perf data file.
*/
evlist__for_each_entry(session->evlist, evsel) {
if (strstr(evsel->name, "arm_spe") &&
if (strstr(evsel__name(evsel), "arm_spe") &&
!(sample_type & PERF_SAMPLE_DATA_SRC)) {
evsel->core.attr.sample_type |= PERF_SAMPLE_DATA_SRC;
sample_type |= PERF_SAMPLE_DATA_SRC;
@ -609,7 +610,7 @@ static void report__warn_kptr_restrict(const struct report *rep)
return;
if (kernel_map == NULL ||
(map__dso(kernel_map)->hit &&
(dso__hit(map__dso(kernel_map)) &&
(kernel_kmap->ref_reloc_sym == NULL ||
kernel_kmap->ref_reloc_sym->addr == 0))) {
const char *desc =
@ -850,7 +851,7 @@ static int maps__fprintf_task_cb(struct map *map, void *data)
prot & PROT_EXEC ? 'x' : '-',
map__flags(map) ? 's' : 'p',
map__pgoff(map),
dso->id.ino, dso->name);
dso__id_const(dso)->ino, dso__name(dso));
if (ret < 0)
return ret;
@ -1694,6 +1695,11 @@ repeat:
else
use_browser = 0;
if (report.data_type && use_browser == 1) {
symbol_conf.annotate_data_member = true;
symbol_conf.annotate_data_sample = true;
}
if (sort_order && strstr(sort_order, "ipc")) {
parse_options_usage(report_usage, options, "s", 1);
goto error;

13
tools/perf/builtin-sched.c
View File

@ -2148,7 +2148,7 @@ static bool is_idle_sample(struct perf_sample *sample,
struct evsel *evsel)
{
/* pid 0 == swapper == idle task */
if (strcmp(evsel__name(evsel), "sched:sched_switch") == 0)
if (evsel__name_is(evsel, "sched:sched_switch"))
return evsel__intval(evsel, sample, "prev_pid") == 0;
return sample->pid == 0;
@ -2375,7 +2375,7 @@ static bool timehist_skip_sample(struct perf_sched *sched,
}
if (sched->idle_hist) {
if (strcmp(evsel__name(evsel), "sched:sched_switch"))
if (!evsel__name_is(evsel, "sched:sched_switch"))
rc = true;
else if (evsel__intval(evsel, sample, "prev_pid") != 0 &&
evsel__intval(evsel, sample, "next_pid") != 0)
@ -2963,8 +2963,11 @@ static int timehist_check_attr(struct perf_sched *sched,
return -1;
}
if (sched->show_callchain && !evsel__has_callchain(evsel)) {
pr_info("Samples do not have callchains.\n");
/* only need to save callchain related to sched_switch event */
if (sched->show_callchain &&
evsel__name_is(evsel, "sched:sched_switch") &&
!evsel__has_callchain(evsel)) {
pr_info("Samples of sched_switch event do not have callchains.\n");
sched->show_callchain = 0;
symbol_conf.use_callchain = 0;
}
@ -3210,7 +3213,7 @@ static int perf_sched__lat(struct perf_sched *sched)
perf_sched__sort_lat(sched);
printf("\n -------------------------------------------------------------------------------------------------------------------------------------------\n");
printf(" Task | Runtime ms | Switches | Avg delay ms | Max delay ms | Max delay start | Max delay end |\n");
printf(" Task | Runtime ms | Count | Avg delay ms | Max delay ms | Max delay start | Max delay end |\n");
printf(" -------------------------------------------------------------------------------------------------------------------------------------------\n");
next = rb_first_cached(&sched->sorted_atom_root);

86
tools/perf/builtin-script.c
View File

@ -32,6 +32,7 @@
#include "util/time-utils.h"
#include "util/path.h"
#include "util/event.h"
#include "util/mem-info.h"
#include "ui/ui.h"
#include "print_binary.h"
#include "print_insn.h"
@ -136,6 +137,7 @@ enum perf_output_field {
PERF_OUTPUT_RETIRE_LAT = 1ULL << 40,
PERF_OUTPUT_DSOFF = 1ULL << 41,
PERF_OUTPUT_DISASM = 1ULL << 42,
PERF_OUTPUT_BRSTACKDISASM = 1ULL << 43,
};
struct perf_script {
@ -210,6 +212,7 @@ struct output_option {
{.str = "vcpu", .field = PERF_OUTPUT_VCPU},
{.str = "cgroup", .field = PERF_OUTPUT_CGROUP},
{.str = "retire_lat", .field = PERF_OUTPUT_RETIRE_LAT},
{.str = "brstackdisasm", .field = PERF_OUTPUT_BRSTACKDISASM},
};
enum {
@ -510,7 +513,8 @@ static int evsel__check_attr(struct evsel *evsel, struct perf_session *session)
"selected. Hence, no address to lookup the source line number.\n");
return -EINVAL;
}
if ((PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN)) && !allow_user_set &&
if ((PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN) || PRINT_FIELD(BRSTACKDISASM))
&& !allow_user_set &&
!(evlist__combined_branch_type(session->evlist) & PERF_SAMPLE_BRANCH_ANY)) {
pr_err("Display of branch stack assembler requested, but non all-branch filter set\n"
"Hint: run 'perf record -b ...'\n");
@ -1014,11 +1018,11 @@ static int perf_sample__fprintf_brstackoff(struct perf_sample *sample,
to = entries[i].to;
if (thread__find_map_fb(thread, sample->cpumode, from, &alf) &&
!map__dso(alf.map)->adjust_symbols)
!dso__adjust_symbols(map__dso(alf.map)))
from = map__dso_map_ip(alf.map, from);
if (thread__find_map_fb(thread, sample->cpumode, to, &alt) &&
!map__dso(alt.map)->adjust_symbols)
!dso__adjust_symbols(map__dso(alt.map)))
to = map__dso_map_ip(alt.map, to);
printed += fprintf(fp, " 0x%"PRIx64, from);
@ -1079,7 +1083,7 @@ static int grab_bb(u8 *buffer, u64 start, u64 end,
pr_debug("\tcannot resolve %" PRIx64 "-%" PRIx64 "\n", start, end);
goto out;
}
if (dso->data.status == DSO_DATA_STATUS_ERROR) {
if (dso__data(dso)->status == DSO_DATA_STATUS_ERROR) {
pr_debug("\tcannot resolve %" PRIx64 "-%" PRIx64 "\n", start, end);
goto out;
}
@ -1091,7 +1095,7 @@ static int grab_bb(u8 *buffer, u64 start, u64 end,
len = dso__data_read_offset(dso, machine, offset, (u8 *)buffer,
end - start + MAXINSN);
*is64bit = dso->is_64_bit;
*is64bit = dso__is_64_bit(dso);
if (len <= 0)
pr_debug("\tcannot fetch code for block at %" PRIx64 "-%" PRIx64 "\n",
start, end);
@ -1162,6 +1166,31 @@ out:
return ret;
}
static int any_dump_insn(struct perf_event_attr *attr __maybe_unused,
struct perf_insn *x, uint64_t ip,
u8 *inbuf, int inlen, int *lenp,
FILE *fp)
{
#ifdef HAVE_LIBCAPSTONE_SUPPORT
if (PRINT_FIELD(BRSTACKDISASM)) {
int printed = fprintf_insn_asm(x->machine, x->thread, x->cpumode, x->is64bit,
(uint8_t *)inbuf, inlen, ip, lenp,
PRINT_INSN_IMM_HEX, fp);
if (printed > 0)
return printed;
}
#endif
return fprintf(fp, "%s", dump_insn(x, ip, inbuf, inlen, lenp));
}
static int add_padding(FILE *fp, int printed, int padding)
{
if (printed >= 0 && printed < padding)
printed += fprintf(fp, "%*s", padding - printed, "");
return printed;
}
static int ip__fprintf_jump(uint64_t ip, struct branch_entry *en,
struct perf_insn *x, u8 *inbuf, int len,
int insn, FILE *fp, int *total_cycles,
@ -1169,8 +1198,10 @@ static int ip__fprintf_jump(uint64_t ip, struct branch_entry *en,
struct thread *thread)
{
int ilen = 0;
int printed = fprintf(fp, "\t%016" PRIx64 "\t%-30s\t", ip,
dump_insn(x, ip, inbuf, len, &ilen));
int printed = fprintf(fp, "\t%016" PRIx64 "\t", ip);
printed += add_padding(fp, any_dump_insn(attr, x, ip, inbuf, len, &ilen, fp), 30);
printed += fprintf(fp, "\t");
if (PRINT_FIELD(BRSTACKINSNLEN))
printed += fprintf(fp, "ilen: %d\t", ilen);
@ -1262,6 +1293,7 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
nr = max_blocks + 1;
x.thread = thread;
x.machine = machine;
x.cpu = sample->cpu;
printed += fprintf(fp, "%c", '\n');
@ -1312,8 +1344,8 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
break;
} else {
ilen = 0;
printed += fprintf(fp, "\t%016" PRIx64 "\t%s", ip,
dump_insn(&x, ip, buffer + off, len - off, &ilen));
printed += fprintf(fp, "\t%016" PRIx64 "\t", ip);
printed += any_dump_insn(attr, &x, ip, buffer + off, len - off, &ilen, fp);
if (PRINT_FIELD(BRSTACKINSNLEN))
printed += fprintf(fp, "\tilen: %d", ilen);
printed += fprintf(fp, "\n");
@ -1360,8 +1392,8 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
if (len <= 0)
goto out;
ilen = 0;
printed += fprintf(fp, "\t%016" PRIx64 "\t%s", sample->ip,
dump_insn(&x, sample->ip, buffer, len, &ilen));
printed += fprintf(fp, "\t%016" PRIx64 "\t", sample->ip);
printed += any_dump_insn(attr, &x, sample->ip, buffer, len, &ilen, fp);
if (PRINT_FIELD(BRSTACKINSNLEN))
printed += fprintf(fp, "\tilen: %d", ilen);
printed += fprintf(fp, "\n");
@ -1371,8 +1403,8 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
}
for (off = 0; off <= end - start; off += ilen) {
ilen = 0;
printed += fprintf(fp, "\t%016" PRIx64 "\t%s", start + off,
dump_insn(&x, start + off, buffer + off, len - off, &ilen));
printed += fprintf(fp, "\t%016" PRIx64 "\t", start + off);
printed += any_dump_insn(attr, &x, start + off, buffer + off, len - off, &ilen, fp);
if (PRINT_FIELD(BRSTACKINSNLEN))
printed += fprintf(fp, "\tilen: %d", ilen);
printed += fprintf(fp, "\n");
@ -1517,7 +1549,8 @@ void script_fetch_insn(struct perf_sample *sample, struct thread *thread,
static int perf_sample__fprintf_insn(struct perf_sample *sample,
struct perf_event_attr *attr,
struct thread *thread,
struct machine *machine, FILE *fp)
struct machine *machine, FILE *fp,
struct addr_location *al)
{
int printed = 0;
@ -1531,9 +1564,9 @@ static int perf_sample__fprintf_insn(struct perf_sample *sample,
}
if (PRINT_FIELD(DISASM) && sample->insn_len) {
printed += fprintf(fp, "\t\t");
printed += sample__fprintf_insn_asm(sample, thread, machine, fp);
printed += sample__fprintf_insn_asm(sample, thread, machine, fp, al);
}
if (PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN))
if (PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN) || PRINT_FIELD(BRSTACKDISASM))
printed += perf_sample__fprintf_brstackinsn(sample, thread, attr, machine, fp);
return printed;
@ -1606,7 +1639,7 @@ static int perf_sample__fprintf_bts(struct perf_sample *sample,
if (print_srcline_last)
printed += map__fprintf_srcline(al->map, al->addr, "\n ", fp);
printed += perf_sample__fprintf_insn(sample, attr, thread, machine, fp);
printed += perf_sample__fprintf_insn(sample, attr, thread, machine, fp, al);
printed += fprintf(fp, "\n");
if (PRINT_FIELD(SRCCODE)) {
int ret = map__fprintf_srccode(al->map, al->addr, stdout,
@ -2018,13 +2051,18 @@ static int evlist__max_name_len(struct evlist *evlist)
static int data_src__fprintf(u64 data_src, FILE *fp)
{
struct mem_info mi = { .data_src.val = data_src };
struct mem_info *mi = mem_info__new();
char decode[100];
char out[100];
static int maxlen;
int len;
perf_script__meminfo_scnprintf(decode, 100, &mi);
if (!mi)
return -ENOMEM;
mem_info__data_src(mi)->val = data_src;
perf_script__meminfo_scnprintf(decode, 100, mi);
mem_info__put(mi);
len = scnprintf(out, 100, "%16" PRIx64 " %s", data_src, decode);
if (maxlen < len)
@ -2259,7 +2297,7 @@ static void process_event(struct perf_script *script,
if (evsel__is_bpf_output(evsel) && PRINT_FIELD(BPF_OUTPUT))
perf_sample__fprintf_bpf_output(sample, fp);
perf_sample__fprintf_insn(sample, attr, thread, machine, fp);
perf_sample__fprintf_insn(sample, attr, thread, machine, fp, al);
if (PRINT_FIELD(PHYS_ADDR))
fprintf(fp, "%16" PRIx64, sample->phys_addr);
@ -2465,7 +2503,7 @@ static int process_attr(struct perf_tool *tool, union perf_event *event,
evsel = evlist__last(*pevlist);
if (!evsel->priv) {
if (scr->per_event_dump) {
if (scr->per_event_dump) {
evsel->priv = evsel_script__new(evsel, scr->session->data);
if (!evsel->priv)
return -ENOMEM;
@ -3471,7 +3509,7 @@ static int check_ev_match(char *dir_name, char *scriptname,
match = 0;
evlist__for_each_entry(session->evlist, pos) {
if (!strcmp(evsel__name(pos), evname)) {
if (evsel__name_is(pos, evname)) {
match = 1;
break;
}
@ -3806,7 +3844,7 @@ static int parse_insn_trace(const struct option *opt __maybe_unused,
if (ret < 0)
return ret;
itrace_parse_synth_opts(opt, "i0ns", 0);
itrace_parse_synth_opts(opt, "i0nse", 0);
symbol_conf.nanosecs = true;
return 0;
}
@ -3939,7 +3977,7 @@ int cmd_script(int argc, const char **argv)
"Fields: comm,tid,pid,time,cpu,event,trace,ip,sym,dso,dsoff,"
"addr,symoff,srcline,period,iregs,uregs,brstack,"
"brstacksym,flags,data_src,weight,bpf-output,brstackinsn,"
"brstackinsnlen,brstackoff,callindent,insn,disasm,insnlen,synth,"
"brstackinsnlen,brstackdisasm,brstackoff,callindent,insn,disasm,insnlen,synth,"
"phys_addr,metric,misc,srccode,ipc,tod,data_page_size,"
"code_page_size,ins_lat,machine_pid,vcpu,cgroup,retire_lat",
parse_output_fields),

52
tools/perf/builtin-stat.c
View File

@ -164,26 +164,6 @@ static struct perf_stat_config stat_config = {
.iostat_run = false,
};
static bool cpus_map_matched(struct evsel *a, struct evsel *b)
{
if (!a->core.cpus && !b->core.cpus)
return true;
if (!a->core.cpus || !b->core.cpus)
return false;
if (perf_cpu_map__nr(a->core.cpus) != perf_cpu_map__nr(b->core.cpus))
return false;
for (int i = 0; i < perf_cpu_map__nr(a->core.cpus); i++) {
if (perf_cpu_map__cpu(a->core.cpus, i).cpu !=
perf_cpu_map__cpu(b->core.cpus, i).cpu)
return false;
}
return true;
}
static void evlist__check_cpu_maps(struct evlist *evlist)
{
struct evsel *evsel, *warned_leader = NULL;
@ -194,7 +174,7 @@ static void evlist__check_cpu_maps(struct evlist *evlist)
/* Check that leader matches cpus with each member. */
if (leader == evsel)
continue;
if (cpus_map_matched(leader, evsel))
if (perf_cpu_map__equal(leader->core.cpus, evsel->core.cpus))
continue;
/* If there's mismatch disable the group and warn user. */
@ -1319,10 +1299,9 @@ static int cpu__get_cache_id_from_map(struct perf_cpu cpu, char *map)
* be the first online CPU in the cache domain else use the
* first online CPU of the cache domain as the ID.
*/
if (perf_cpu_map__has_any_cpu_or_is_empty(cpu_map))
id = perf_cpu_map__min(cpu_map).cpu;
if (id == -1)
id = cpu.cpu;
else
id = perf_cpu_map__cpu(cpu_map, 0).cpu;
/* Free the perf_cpu_map used to find the cache ID */
perf_cpu_map__put(cpu_map);
@ -1642,7 +1621,7 @@ static int perf_stat_init_aggr_mode(void)
* taking the highest cpu number to be the size of
* the aggregation translate cpumap.
*/
if (!perf_cpu_map__has_any_cpu_or_is_empty(evsel_list->core.user_requested_cpus))
if (!perf_cpu_map__is_any_cpu_or_is_empty(evsel_list->core.user_requested_cpus))
nr = perf_cpu_map__max(evsel_list->core.user_requested_cpus).cpu;
else
nr = 0;
@ -1652,23 +1631,13 @@ static int perf_stat_init_aggr_mode(void)
static void cpu_aggr_map__delete(struct cpu_aggr_map *map)
{
if (map) {
WARN_ONCE(refcount_read(&map->refcnt) != 0,
"cpu_aggr_map refcnt unbalanced\n");
free(map);
}
}
static void cpu_aggr_map__put(struct cpu_aggr_map *map)
{
if (map && refcount_dec_and_test(&map->refcnt))
cpu_aggr_map__delete(map);
free(map);
}
static void perf_stat__exit_aggr_mode(void)
{
cpu_aggr_map__put(stat_config.aggr_map);
cpu_aggr_map__put(stat_config.cpus_aggr_map);
cpu_aggr_map__delete(stat_config.aggr_map);
cpu_aggr_map__delete(stat_config.cpus_aggr_map);
stat_config.aggr_map = NULL;
stat_config.cpus_aggr_map = NULL;
}
@ -2106,6 +2075,7 @@ static int add_default_attributes(void)
stat_config.metric_no_threshold,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events);
}
@ -2139,6 +2109,7 @@ static int add_default_attributes(void)
stat_config.metric_no_threshold,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events);
}
@ -2173,6 +2144,7 @@ static int add_default_attributes(void)
/*metric_no_threshold=*/true,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events) < 0)
return -1;
}
@ -2214,6 +2186,7 @@ static int add_default_attributes(void)
/*metric_no_threshold=*/true,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events) < 0)
return -1;
@ -2334,7 +2307,7 @@ int process_stat_config_event(struct perf_session *session,
perf_event__read_stat_config(&stat_config, &event->stat_config);
if (perf_cpu_map__has_any_cpu_or_is_empty(st->cpus)) {
if (perf_cpu_map__is_empty(st->cpus)) {
if (st->aggr_mode != AGGR_UNSET)
pr_warning("warning: processing task data, aggregation mode not set\n");
} else if (st->aggr_mode != AGGR_UNSET) {
@ -2748,6 +2721,7 @@ int cmd_stat(int argc, const char **argv)
stat_config.metric_no_threshold,
stat_config.user_requested_cpu_list,
stat_config.system_wide,
stat_config.hardware_aware_grouping,
&stat_config.metric_events);
zfree(&metrics);

4
tools/perf/builtin-top.c
View File

@ -129,7 +129,7 @@ static int perf_top__parse_source(struct perf_top *top, struct hist_entry *he)
/*
* We can't annotate with just /proc/kallsyms
*/
if (dso->symtab_type == DSO_BINARY_TYPE__KALLSYMS && !dso__is_kcore(dso)) {
if (dso__symtab_type(dso) == DSO_BINARY_TYPE__KALLSYMS && !dso__is_kcore(dso)) {
pr_err("Can't annotate %s: No vmlinux file was found in the "
"path\n", sym->name);
sleep(1);
@ -182,7 +182,7 @@ static void ui__warn_map_erange(struct map *map, struct symbol *sym, u64 ip)
"Tools: %s\n\n"
"Not all samples will be on the annotation output.\n\n"
"Please report to linux-kernel@vger.kernel.org\n",
ip, dso->long_name, dso__symtab_origin(dso),
ip, dso__long_name(dso), dso__symtab_origin(dso),
map__start(map), map__end(map), sym->start, sym->end,
sym->binding == STB_GLOBAL ? 'g' :
sym->binding == STB_LOCAL ? 'l' : 'w', sym->name,

35
tools/perf/builtin-trace.c
View File

@ -947,6 +947,15 @@ static const struct syscall_fmt syscall_fmts[] = {
.arg = { [1] = STRARRAY(op, epoll_ctl_ops), }, },
{ .name = "eventfd2",
.arg = { [1] = { .scnprintf = SCA_EFD_FLAGS, /* flags */ }, }, },
{ .name = "faccessat",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dirfd */ },
[1] = { .scnprintf = SCA_FILENAME, /* pathname */ },
[2] = { .scnprintf = SCA_ACCMODE, /* mode */ }, }, },
{ .name = "faccessat2",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dirfd */ },
[1] = { .scnprintf = SCA_FILENAME, /* pathname */ },
[2] = { .scnprintf = SCA_ACCMODE, /* mode */ },
[3] = { .scnprintf = SCA_FACCESSAT2_FLAGS, /* flags */ }, }, },
{ .name = "fchmodat",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* fd */ }, }, },
{ .name = "fchownat",
@ -969,7 +978,6 @@ static const struct syscall_fmt syscall_fmts[] = {
[1] = { .scnprintf = SCA_FILENAME, /* path */ },
[2] = { .scnprintf = SCA_FSPICK_FLAGS, /* flags */ }, }, },
{ .name = "fstat", .alias = "newfstat", },
{ .name = "fstatat", .alias = "newfstatat", },
{ .name = "futex",
.arg = { [1] = { .scnprintf = SCA_FUTEX_OP, /* op */ },
[5] = { .scnprintf = SCA_FUTEX_VAL3, /* val3 */ }, }, },
@ -1049,8 +1057,12 @@ static const struct syscall_fmt syscall_fmts[] = {
.arg = { [3] = { .scnprintf = SCA_MREMAP_FLAGS, /* flags */ }, }, },
{ .name = "name_to_handle_at",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dfd */ }, }, },
{ .name = "newfstatat",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dfd */ }, }, },
{ .name = "nanosleep",
.arg = { [0] = { .scnprintf = SCA_TIMESPEC, /* req */ }, }, },
{ .name = "newfstatat", .alias = "fstatat",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dirfd */ },
[1] = { .scnprintf = SCA_FILENAME, /* pathname */ },
[3] = { .scnprintf = SCA_FS_AT_FLAGS, /* flags */ }, }, },
{ .name = "open",
.arg = { [1] = { .scnprintf = SCA_OPEN_FLAGS, /* flags */ }, }, },
{ .name = "open_by_handle_at",
@ -1142,7 +1154,7 @@ static const struct syscall_fmt syscall_fmts[] = {
{ .name = "stat", .alias = "newstat", },
{ .name = "statx",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* fdat */ },
[2] = { .scnprintf = SCA_STATX_FLAGS, /* flags */ } ,
[2] = { .scnprintf = SCA_FS_AT_FLAGS, /* flags */ } ,
[3] = { .scnprintf = SCA_STATX_MASK, /* mask */ }, }, },
{ .name = "swapoff",
.arg = { [0] = { .scnprintf = SCA_FILENAME, /* specialfile */ }, }, },
@ -1160,7 +1172,9 @@ static const struct syscall_fmt syscall_fmts[] = {
.arg = { [0] = { .scnprintf = SCA_FILENAME, /* name */ }, }, },
{ .name = "uname", .alias = "newuname", },
{ .name = "unlinkat",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dfd */ }, }, },
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dfd */ },
[1] = { .scnprintf = SCA_FILENAME, /* pathname */ },
[2] = { .scnprintf = SCA_FS_AT_FLAGS, /* flags */ }, }, },
{ .name = "utimensat",
.arg = { [0] = { .scnprintf = SCA_FDAT, /* dirfd */ }, }, },
{ .name = "wait4", .errpid = true,
@ -2903,7 +2917,7 @@ static void print_location(FILE *f, struct perf_sample *sample,
{
if ((verbose > 0 || print_dso) && al->map)
fprintf(f, "%s@", map__dso(al->map)->long_name);
fprintf(f, "%s@", dso__long_name(map__dso(al->map)));
if ((verbose > 0 || print_sym) && al->sym)
fprintf(f, "%s+0x%" PRIx64, al->sym->name,
@ -4869,6 +4883,11 @@ int cmd_trace(int argc, const char **argv)
if (!trace.trace_syscalls)
goto skip_augmentation;
if ((argc >= 1) && (strcmp(argv[0], "record") == 0)) {
pr_debug("Syscall augmentation fails with record, disabling augmentation");
goto skip_augmentation;
}
trace.skel = augmented_raw_syscalls_bpf__open();
if (!trace.skel) {
pr_debug("Failed to open augmented syscalls BPF skeleton");
@ -4902,7 +4921,7 @@ int cmd_trace(int argc, const char **argv)
goto out;
}
trace.syscalls.events.bpf_output = evlist__last(trace.evlist);
assert(!strcmp(evsel__name(trace.syscalls.events.bpf_output), "__augmented_syscalls__"));
assert(evsel__name_is(trace.syscalls.events.bpf_output, "__augmented_syscalls__"));
skip_augmentation:
#endif
err = -1;
@ -4959,7 +4978,7 @@ skip_augmentation:
*/
if (trace.syscalls.events.bpf_output) {
evlist__for_each_entry(trace.evlist, evsel) {
bool raw_syscalls_sys_exit = strcmp(evsel__name(evsel), "raw_syscalls:sys_exit") == 0;
bool raw_syscalls_sys_exit = evsel__name_is(evsel, "raw_syscalls:sys_exit");
if (raw_syscalls_sys_exit) {
trace.raw_augmented_syscalls = true;

4
tools/perf/builtin.h
View File

@ -2,8 +2,10 @@
#ifndef BUILTIN_H
#define BUILTIN_H
struct cmdnames;
void list_common_cmds_help(void);
const char *help_unknown_cmd(const char *cmd);
const char *help_unknown_cmd(const char *cmd, struct cmdnames *main_cmds);
int cmd_annotate(int argc, const char **argv);
int cmd_bench(int argc, const char **argv);

23
tools/perf/check-headers.sh
View File

@ -9,23 +9,15 @@ FILES=(
"include/uapi/linux/const.h"
"include/uapi/drm/drm.h"
"include/uapi/drm/i915_drm.h"
"include/uapi/linux/bits.h"
"include/uapi/linux/fadvise.h"
"include/uapi/linux/fcntl.h"
"include/uapi/linux/fs.h"
"include/uapi/linux/fscrypt.h"
"include/uapi/linux/kcmp.h"
"include/uapi/linux/kvm.h"
"include/uapi/linux/in.h"
"include/uapi/linux/mount.h"
"include/uapi/linux/openat2.h"
"include/uapi/linux/perf_event.h"
"include/uapi/linux/prctl.h"
"include/uapi/linux/sched.h"
"include/uapi/linux/seccomp.h"
"include/uapi/linux/stat.h"
"include/uapi/linux/usbdevice_fs.h"
"include/uapi/linux/vhost.h"
"include/uapi/sound/asound.h"
"include/linux/bits.h"
"include/vdso/bits.h"
"include/linux/const.h"
@ -38,9 +30,7 @@ FILES=(
"arch/x86/include/asm/cpufeatures.h"
"arch/x86/include/asm/inat_types.h"
"arch/x86/include/asm/emulate_prefix.h"
"arch/x86/include/asm/irq_vectors.h"
"arch/x86/include/asm/msr-index.h"
"arch/x86/include/uapi/asm/prctl.h"
"arch/x86/lib/x86-opcode-map.txt"
"arch/x86/tools/gen-insn-attr-x86.awk"
"arch/arm/include/uapi/asm/perf_regs.h"
@ -97,7 +87,18 @@ SYNC_CHECK_FILES=(
declare -a BEAUTY_FILES
BEAUTY_FILES=(
"arch/x86/include/asm/irq_vectors.h"
"arch/x86/include/uapi/asm/prctl.h"
"include/linux/socket.h"
"include/uapi/linux/fcntl.h"
"include/uapi/linux/fs.h"
"include/uapi/linux/mount.h"
"include/uapi/linux/prctl.h"
"include/uapi/linux/sched.h"
"include/uapi/linux/stat.h"
"include/uapi/linux/usbdevice_fs.h"
"include/uapi/linux/vhost.h"
"include/uapi/sound/asound.h"
)
declare -a FAILURES

2
tools/perf/perf-archive.sh
View File

@ -34,7 +34,7 @@ if [ $UNPACK -eq 1 ]; then
TARGET=`find . -regex "\./perf.*\.tar\.bz2"`
TARGET_NUM=`echo -n "$TARGET" | grep -c '^'`
if [ -z "$TARGET" -o $TARGET_NUM -gt 1 ]; then
if [ -z "$TARGET" ] || [ $TARGET_NUM -gt 1 ]; then
echo -e "Error: $TARGET_NUM files found for unpacking:\n$TARGET"
echo "Provide the requested file as an argument"
exit 1

23
tools/perf/perf-completion.sh
View File

@ -108,6 +108,8 @@ __perf__ltrim_colon_completions()
__perfcomp ()
{
# Expansion of spaces to array is deliberate.
# shellcheck disable=SC2207
COMPREPLY=( $( compgen -W "$1" -- "$2" ) )
}
@ -127,13 +129,13 @@ __perf_prev_skip_opts ()
let i=cword-1
cmds_=$($cmd $1 --list-cmds)
prev_skip_opts=()
prev_skip_opts=""
while [ $i -ge 0 ]; do
if [[ ${words[i]} == $1 ]]; then
if [[ ${words[i]} == "$1" ]]; then
return
fi
for cmd_ in $cmds_; do
if [[ ${words[i]} == $cmd_ ]]; then
if [[ ${words[i]} == "$cmd_" ]]; then
prev_skip_opts=${words[i]}
return
fi
@ -164,9 +166,10 @@ __perf_main ()
$prev_skip_opts == @(record|stat|top) ]]; then
local cur1=${COMP_WORDS[COMP_CWORD]}
local raw_evts=$($cmd list --raw-dump hw sw cache tracepoint pmu sdt)
local raw_evts
local arr s tmp result cpu_evts
raw_evts=$($cmd list --raw-dump hw sw cache tracepoint pmu sdt)
# aarch64 doesn't have /sys/bus/event_source/devices/cpu/events
if [[ `uname -m` != aarch64 ]]; then
cpu_evts=$(ls /sys/bus/event_source/devices/cpu/events)
@ -175,10 +178,12 @@ __perf_main ()
if [[ "$cur1" == */* && ${cur1#*/} =~ ^[A-Z] ]]; then
OLD_IFS="$IFS"
IFS=" "
# Expansion of spaces to array is deliberate.
# shellcheck disable=SC2206
arr=($raw_evts)
IFS="$OLD_IFS"
for s in ${arr[@]}
for s in "${arr[@]}"
do
if [[ "$s" == *cpu/* ]]; then
tmp=${s#*cpu/}
@ -200,11 +205,13 @@ __perf_main ()
fi
elif [[ $prev == @("--pfm-events") &&
$prev_skip_opts == @(record|stat|top) ]]; then
local evts=$($cmd list --raw-dump pfm)
local evts
evts=$($cmd list --raw-dump pfm)
__perfcomp "$evts" "$cur"
elif [[ $prev == @("-M"|"--metrics") &&
$prev_skip_opts == @(stat) ]]; then
local metrics=$($cmd list --raw-dump metric metricgroup)
local metrics
metrics=$($cmd list --raw-dump metric metricgroup)
__perfcomp "$metrics" "$cur"
else
# List subcommands for perf commands
@ -278,6 +285,8 @@ if [[ -n ${ZSH_VERSION-} ]]; then
let cword=CURRENT-1
emulate ksh -c __perf_main
let _ret && _default && _ret=0
# _ret is only assigned 0 or 1, disable inaccurate analysis.
# shellcheck disable=SC2152
return _ret
}

23
tools/perf/perf.c
View File

@ -18,6 +18,7 @@
#include <subcmd/run-command.h>
#include "util/parse-events.h"
#include <subcmd/parse-options.h>
#include <subcmd/help.h>
#include "util/debug.h"
#include "util/event.h"
#include "util/util.h" // usage()
@ -458,7 +459,7 @@ static int libperf_print(enum libperf_print_level level,
int main(int argc, const char **argv)
{
int err;
int err, done_help = 0;
const char *cmd;
char sbuf[STRERR_BUFSIZE];
@ -557,22 +558,32 @@ int main(int argc, const char **argv)
pthread__block_sigwinch();
while (1) {
static int done_help;
run_argv(&argc, &argv);
if (errno != ENOENT)
break;
if (!done_help) {
cmd = argv[0] = help_unknown_cmd(cmd);
struct cmdnames main_cmds = {};
for (unsigned int i = 0; i < ARRAY_SIZE(commands); i++) {
add_cmdname(&main_cmds,
commands[i].cmd,
strlen(commands[i].cmd));
}
cmd = argv[0] = help_unknown_cmd(cmd, &main_cmds);
clean_cmdnames(&main_cmds);
done_help = 1;
if (!cmd)
break;
} else
break;
}
fprintf(stderr, "Failed to run command '%s': %s\n",
cmd, str_error_r(errno, sbuf, sizeof(sbuf)));
if (cmd) {
fprintf(stderr, "Failed to run command '%s': %s\n",
cmd, str_error_r(errno, sbuf, sizeof(sbuf)));
}
out:
if (debug_fp)
fclose(debug_fp);

4
tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
View File

@ -9,7 +9,9 @@
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
"ArchStdEvent": "L1D_CACHE_INVAL",
"Errata": "Errata AC03_CPU_41",
"BriefDescription": "L1D cache invalidate. Impacted by errata -"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"

4
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json
View File

@ -9,7 +9,9 @@
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
"ArchStdEvent": "L1D_CACHE_INVAL",
"Errata": "Errata AC04_CPU_1",
"BriefDescription": "L1D cache invalidate. Impacted by errata -"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"

28
tools/perf/pmu-events/arch/s390/cf_z16/transaction.json
View File

@ -2,71 +2,71 @@
{
"BriefDescription": "Transaction count",
"MetricName": "transaction",
"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0"
},
{
"BriefDescription": "Cycles per Instruction",
"MetricName": "cpi",
"MetricExpr": "CPU_CYCLES / INSTRUCTIONS"
"MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Problem State Instruction Ratio",
"MetricName": "prbstate",
"MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100"
"MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Level One Miss per 100 Instructions",
"MetricName": "l1mp",
"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 2 cache",
"MetricName": "l2p",
"MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
"MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
"MetricName": "l3p",
"MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
"MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
"MetricName": "l4lp",
"MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
"MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0"
},
{
"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
"MetricName": "l4rp",
"MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
"MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0"
},
{
"BriefDescription": "Percentage sourced from memory",
"MetricName": "memp",
"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0"
},
{
"BriefDescription": "Cycles per Instructions from Finite cache/memory",
"MetricName": "finite_cpi",
"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"
"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0"
},
{
"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
"MetricName": "est_cpi",
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0"
},
{
"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
"MetricName": "scpl1m",
"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0"
},
{
"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
"MetricName": "tlb_percent",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0"
},
{
"BriefDescription": "Estimated Cycles per TLB Miss",
"MetricName": "tlb_miss",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0"
}
]

2
tools/perf/pmu-events/arch/s390/mapfile.csv
View File

@ -5,4 +5,4 @@ Family-model,Version,Filename,EventType
^IBM.296[45].*[13]\.[1-5].[[:xdigit:]]+$,1,cf_z13,core
^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$,3,cf_z14,core
^IBM.856[12].*3\.6.[[:xdigit:]]+$,3,cf_z15,core
^IBM.393[12].*3\.7.[[:xdigit:]]+$,3,cf_z16,core
^IBM.393[12].*$,3,cf_z16,core

1 Family-model Version Filename EventType
5 ^IBM.296[45].*[13]\.[1-5].[[:xdigit:]]+$ 1 cf_z13 core
6 ^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$ 3 cf_z14 core
7 ^IBM.856[12].*3\.6.[[:xdigit:]]+$ 3 cf_z15 core
8 ^IBM.393[12].*3\.7.[[:xdigit:]]+$ ^IBM.393[12].*$ 3 cf_z16 core

93
tools/perf/pmu-events/arch/x86/amdzen5/branch-prediction.json Normal file
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@ -0,0 +1,93 @@
[
{
"EventName": "bp_l1_tlb_miss_l2_tlb_hit",
"EventCode": "0x84",
"BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
"UMask": "0x01"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
"UMask": "0x02"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
"UMask": "0x04"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x08"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
"UMask": "0x0f"
},
{
"EventName": "bp_l2_btb_correct",
"EventCode": "0x8b",
"BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
},
{
"EventName": "bp_dyn_ind_pred",
"EventCode": "0x8e",
"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
},
{
"EventName": "bp_de_redirect",
"EventCode": "0x91",
"BriefDescription": "Number of times an early redirect is sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."
},
{
"EventName": "bp_l1_tlb_fetch_hit.if4k",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x01"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if2m",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
"UMask": "0x02"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if1g",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
"UMask": "0x04"
},
{
"EventName": "bp_l1_tlb_fetch_hit.all",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
"UMask": "0x07"
},
{
"EventName": "bp_redirects.resync",
"EventCode": "0x9f",
"BriefDescription": "Redirects of the branch predictor caused by resyncs.",
"UMask": "0x01"
},
{
"EventName": "bp_redirects.ex_redir",
"EventCode": "0x9f",
"BriefDescription": "Redirects of the branch predictor caused by mispredicts.",
"UMask": "0x02"
},
{
"EventName": "bp_redirects.all",
"EventCode": "0x9f",
"BriefDescription": "Redirects of the branch predictor."
}
]

115
tools/perf/pmu-events/arch/x86/amdzen5/decode.json Normal file
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@ -0,0 +1,115 @@
[
{
"EventName": "de_op_queue_empty",
"EventCode": "0xa9",
"BriefDescription": "Cycles where the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough."
},
{
"EventName": "de_src_op_disp.x86_decoder",
"EventCode": "0xaa",
"BriefDescription": "Ops dispatched from x86 decoder.",
"UMask": "0x01"
},
{
"EventName": "de_src_op_disp.op_cache",
"EventCode": "0xaa",
"BriefDescription": "Ops dispatched from op cache.",
"UMask": "0x02"
},
{
"EventName": "de_src_op_disp.all",
"EventCode": "0xaa",
"BriefDescription": "Ops dispatched from any source.",
"UMask": "0x07"
},
{
"EventName": "de_dis_ops_from_decoder.any_fp_dispatch",
"EventCode": "0xab",
"BriefDescription": "Number of ops dispatched to the floating-point unit.",
"UMask": "0x04"
},
{
"EventName": "de_dis_ops_from_decoder.any_integer_dispatch",
"EventCode": "0xab",
"BriefDescription": "Number of ops dispatched to the integer execution unit.",
"UMask": "0x08"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to an integer physical register file resource stall.",
"UMask": "0x01"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a lack of load queue tokens.",
"UMask": "0x02"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a lack of store queue tokens.",
"UMask": "0x04"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc",
"EventCode": "0xae",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a taken branch buffer resource stall.",
"UMask": "0x10"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a floating-point non-schedulable queue token stall.",
"UMask": "0x40"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.al_tokens",
"EventCode": "0xaf",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of ALU tokens.",
"UMask": "0x01"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ag_tokens",
"EventCode": "0xaf",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of agen tokens.",
"UMask": "0x02"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ex_flush_recovery",
"EventCode": "0xaf",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a pending integer execution flush recovery.",
"UMask": "0x04"
},
{
"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.retq",
"EventCode": "0xaf",
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens.",
"UMask": "0x20"
},
{
"EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts dispatch slots left empty because the front-end did not supply ops.",
"UMask": "0x01"
},
{
"EventName": "de_no_dispatch_per_slot.backend_stalls",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts ops unable to dispatch because of back-end stalls.",
"UMask": "0x1e"
},
{
"EventName": "de_no_dispatch_per_slot.smt_contention",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread.",
"UMask": "0x60"
},
{
"EventName": "de_additional_resource_stalls.dispatch_stalls",
"EventCode": "0x1a2",
"BriefDescription": "Counts additional cycles where dispatch is stalled due to a lack of dispatch resources.",
"UMask": "0x30"
}
]

174
tools/perf/pmu-events/arch/x86/amdzen5/execution.json Normal file
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@ -0,0 +1,174 @@
[
{
"EventName": "ex_ret_instr",
"EventCode": "0xc0",
"BriefDescription": "Retired instructions."
},
{
"EventName": "ex_ret_ops",
"EventCode": "0xc1",
"BriefDescription": "Retired macro-ops."
},
{
"EventName": "ex_ret_brn",
"EventCode": "0xc2",
"BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
},
{
"EventName": "ex_ret_brn_misp",
"EventCode": "0xc3",
"BriefDescription": "Retired branch instructions mispredicted."
},
{
"EventName": "ex_ret_brn_tkn",
"EventCode": "0xc4",
"BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
},
{
"EventName": "ex_ret_brn_tkn_misp",
"EventCode": "0xc5",
"BriefDescription": "Retired taken branch instructions mispredicted."
},
{
"EventName": "ex_ret_brn_far",
"EventCode": "0xc6",
"BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
},
{
"EventName": "ex_ret_near_ret",
"EventCode": "0xc8",
"BriefDescription": "Retired near returns (RET or RET Iw)."
},
{
"EventName": "ex_ret_near_ret_mispred",
"EventCode": "0xc9",
"BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
},
{
"EventName": "ex_ret_brn_ind_misp",
"EventCode": "0xca",
"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
},
{
"EventName": "ex_ret_mmx_fp_instr.x87",
"EventCode": "0xcb",
"BriefDescription": "Retired x87 instructions.",
"UMask": "0x01"
},
{
"EventName": "ex_ret_mmx_fp_instr.mmx",
"EventCode": "0xcb",
"BriefDescription": "Retired MMX instructions.",
"UMask": "0x02"
},
{
"EventName": "ex_ret_mmx_fp_instr.sse",
"EventCode": "0xcb",
"BriefDescription": "Retired SSE instructions (includes SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42 and AVX).",
"UMask": "0x04"
},
{
"EventName": "ex_ret_ind_brch_instr",
"EventCode": "0xcc",
"BriefDescription": "Retired indirect branch instructions."
},
{
"EventName": "ex_ret_cond",
"EventCode": "0xd1",
"BriefDescription": "Retired conditional branch instructions."
},
{
"EventName": "ex_div_busy",
"EventCode": "0xd3",
"BriefDescription": "Number of cycles the divider is busy."
},
{
"EventName": "ex_div_count",
"EventCode": "0xd4",
"BriefDescription": "Divide ops executed."
},
{
"EventName": "ex_no_retire.empty",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
"UMask": "0x01"
},
{
"EventName": "ex_no_retire.not_complete",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",
"UMask": "0x02"
},
{
"EventName": "ex_no_retire.other",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",
"UMask": "0x08"
},
{
"EventName": "ex_no_retire.thread_not_selected",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",
"UMask": "0x10"
},
{
"EventName": "ex_no_retire.load_not_complete",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",
"UMask": "0xa2"
},
{
"EventName": "ex_no_retire.all",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire for any reason.",
"UMask": "0x1b"
},
{
"EventName": "ex_ret_ucode_instr",
"EventCode": "0x1c1",
"BriefDescription": "Retired microcoded instructions."
},
{
"EventName": "ex_ret_ucode_ops",
"EventCode": "0x1c2",
"BriefDescription": "Retired microcode ops."
},
{
"EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
"EventCode": "0x1c7",
"BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
},
{
"EventName": "ex_ret_uncond_brnch_instr_mispred",
"EventCode": "0x1c8",
"BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
},
{
"EventName": "ex_ret_uncond_brnch_instr",
"EventCode": "0x1c9",
"BriefDescription": "Retired unconditional branch instructions."
},
{
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
"EventCode": "0x1cf",
"BriefDescription": "Ops tagged by IBS.",
"UMask": "0x01"
},
{
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
"EventCode": "0x1cf",
"BriefDescription": "Ops tagged by IBS that retired.",
"UMask": "0x02"
},
{
"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
"EventCode": "0x1cf",
"BriefDescription": "Ops not tagged by IBS due to a previous tagged op that has not yet signaled interrupt.",
"UMask": "0x04"
},
{
"EventName": "ex_ret_fused_instr",
"EventCode": "0x1d0",
"BriefDescription": "Retired fused instructions."
}
]

812
tools/perf/pmu-events/arch/x86/amdzen5/floating-point.json Normal file
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@ -0,0 +1,812 @@
[
{
"EventName": "fp_ret_x87_fp_ops.add_sub_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point add and subtract ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ret_x87_fp_ops.mul_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point multiply ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ret_x87_fp_ops.div_sqrt_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point divide and square root ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ret_x87_fp_ops.all",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point ops of all types.",
"UMask": "0x07"
},
{
"EventName": "fp_ret_sse_avx_ops.add_sub_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point add and subtract ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ret_sse_avx_ops.mult_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point multiply ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ret_sse_avx_ops.div_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point divide and square root ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ret_sse_avx_ops.mac_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops).",
"UMask": "0x08"
},
{
"EventName": "fp_ret_sse_avx_ops.bfloat16_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point bfloat16 ops.",
"UMask": "0x20"
},
{
"EventName": "fp_ret_sse_avx_ops.scalar_single_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point scalar single-precision ops.",
"UMask": "0x40"
},
{
"EventName": "fp_ret_sse_avx_ops.packed_single_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point packed single-precision ops.",
"UMask": "0x60"
},
{
"EventName": "fp_ret_sse_avx_ops.scalar_double_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point scalar double-precision ops.",
"UMask": "0x80"
},
{
"EventName": "fp_ret_sse_avx_ops.packed_double_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point packed double-precision ops.",
"UMask": "0xa0"
},
{
"EventName": "fp_ret_sse_avx_ops.all",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_ops_retired_by_width.x87_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired x87 floating-point ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ops_retired_by_width.mmx_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired MMX floating-point ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ops_retired_by_width.scalar_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired scalar floating-point ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ops_retired_by_width.pack_128_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 128-bit floating-point ops.",
"UMask": "0x08"
},
{
"EventName": "fp_ops_retired_by_width.pack_256_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 256-bit floating-point ops.",
"UMask": "0x10"
},
{
"EventName": "fp_ops_retired_by_width.pack_512_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 512-bit floating-point ops.",
"UMask": "0x20"
},
{
"EventName": "fp_ops_retired_by_width.all",
"EventCode": "0x08",
"BriefDescription": "Retired floating-point ops of all widths.",
"UMask": "0x3f"
},
{
"EventName": "fp_ops_retired_by_type.scalar_add",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point add ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ops_retired_by_type.scalar_sub",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point subtract ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ops_retired_by_type.scalar_mul",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point multiply ops.",
"UMask": "0x03"
},
{
"EventName": "fp_ops_retired_by_type.scalar_mac",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ops_retired_by_type.scalar_div",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point divide ops.",
"UMask": "0x05"
},
{
"EventName": "fp_ops_retired_by_type.scalar_sqrt",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point square root ops.",
"UMask": "0x06"
},
{
"EventName": "fp_ops_retired_by_type.scalar_cmp",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point compare ops.",
"UMask": "0x07"
},
{
"EventName": "fp_ops_retired_by_type.scalar_cvt",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point convert ops.",
"UMask": "0x08"
},
{
"EventName": "fp_ops_retired_by_type.scalar_blend",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point blend ops.",
"UMask": "0x09"
},
{
"EventName": "fp_ops_retired_by_type.scalar_other",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "fp_ops_retired_by_type.scalar_all",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_ops_retired_by_type.vector_add",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point add ops.",
"UMask": "0x10"
},
{
"EventName": "fp_ops_retired_by_type.vector_sub",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point subtract ops.",
"UMask": "0x20"
},
{
"EventName": "fp_ops_retired_by_type.vector_mul",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point multiply ops.",
"UMask": "0x30"
},
{
"EventName": "fp_ops_retired_by_type.vector_mac",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "fp_ops_retired_by_type.vector_div",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point divide ops.",
"UMask": "0x50"
},
{
"EventName": "fp_ops_retired_by_type.vector_sqrt",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point square root ops.",
"UMask": "0x60"
},
{
"EventName": "fp_ops_retired_by_type.vector_cmp",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point compare ops.",
"UMask": "0x70"
},
{
"EventName": "fp_ops_retired_by_type.vector_cvt",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point convert ops.",
"UMask": "0x80"
},
{
"EventName": "fp_ops_retired_by_type.vector_blend",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point blend ops.",
"UMask": "0x90"
},
{
"EventName": "fp_ops_retired_by_type.vector_shuffle",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "fp_ops_retired_by_type.vector_logical",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point logical ops.",
"UMask": "0xd0"
},
{
"EventName": "fp_ops_retired_by_type.vector_other",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "fp_ops_retired_by_type.vector_all",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "fp_ops_retired_by_type.all",
"EventCode": "0x0a",
"BriefDescription": "Retired floating-point ops of all types.",
"UMask": "0xff"
},
{
"EventName": "sse_avx_ops_retired.mmx_add",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer add.",
"UMask": "0x01"
},
{
"EventName": "sse_avx_ops_retired.mmx_sub",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer subtract ops.",
"UMask": "0x02"
},
{
"EventName": "sse_avx_ops_retired.mmx_mul",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply ops.",
"UMask": "0x03"
},
{
"EventName": "sse_avx_ops_retired.mmx_mac",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "sse_avx_ops_retired.mmx_cmp",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer compare ops.",
"UMask": "0x07"
},
{
"EventName": "sse_avx_ops_retired.mmx_shift",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer shift ops.",
"UMask": "0x09"
},
{
"EventName": "sse_avx_ops_retired.mmx_mov",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer MOV ops.",
"UMask": "0x0a"
},
{
"EventName": "sse_avx_ops_retired.mmx_shuffle",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "sse_avx_ops_retired.mmx_pack",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer pack ops.",
"UMask": "0x0c"
},
{
"EventName": "sse_avx_ops_retired.mmx_logical",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer logical ops.",
"UMask": "0x0d"
},
{
"EventName": "sse_avx_ops_retired.mmx_other",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "sse_avx_ops_retired.mmx_all",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_add",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer add ops.",
"UMask": "0x10"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_sub",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer subtract ops.",
"UMask": "0x20"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mul",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer multiply ops.",
"UMask": "0x30"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mac",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_aes",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer AES ops.",
"UMask": "0x50"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_sha",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer SHA ops.",
"UMask": "0x60"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_cmp",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer compare ops.",
"UMask": "0x70"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_clm",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer CLM ops.",
"UMask": "0x80"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_shift",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer shift ops.",
"UMask": "0x90"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mov",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer MOV ops.",
"UMask": "0xa0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_shuffle",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_pack",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer pack ops.",
"UMask": "0xc0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_logical",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer logical ops.",
"UMask": "0xd0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_other",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_all",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "sse_avx_ops_retired.all",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE, AVX and MMX integer ops of all types.",
"UMask": "0xff"
},
{
"EventName": "fp_pack_ops_retired.fp128_add",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point add ops.",
"UMask": "0x01"
},
{
"EventName": "fp_pack_ops_retired.fp128_sub",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point subtract ops.",
"UMask": "0x02"
},
{
"EventName": "fp_pack_ops_retired.fp128_mul",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point multiply ops.",
"UMask": "0x03"
},
{
"EventName": "fp_pack_ops_retired.fp128_mac",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "fp_pack_ops_retired.fp128_div",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point divide ops.",
"UMask": "0x05"
},
{
"EventName": "fp_pack_ops_retired.fp128_sqrt",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point square root ops.",
"UMask": "0x06"
},
{
"EventName": "fp_pack_ops_retired.fp128_cmp",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point compare ops.",
"UMask": "0x07"
},
{
"EventName": "fp_pack_ops_retired.fp128_cvt",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point convert ops.",
"UMask": "0x08"
},
{
"EventName": "fp_pack_ops_retired.fp128_blend",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point blend ops.",
"UMask": "0x09"
},
{
"EventName": "fp_pack_ops_retired.fp128_shuffle",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "fp_pack_ops_retired.fp128_logical",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point logical ops.",
"UMask": "0x0d"
},
{
"EventName": "fp_pack_ops_retired.fp128_other",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "fp_pack_ops_retired.fp128_all",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_pack_ops_retired.fp256_add",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point add ops.",
"UMask": "0x10"
},
{
"EventName": "fp_pack_ops_retired.fp256_sub",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point subtract ops.",
"UMask": "0x20"
},
{
"EventName": "fp_pack_ops_retired.fp256_mul",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point multiply ops.",
"UMask": "0x30"
},
{
"EventName": "fp_pack_ops_retired.fp256_mac",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "fp_pack_ops_retired.fp256_div",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point divide ops.",
"UMask": "0x50"
},
{
"EventName": "fp_pack_ops_retired.fp256_sqrt",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point square root ops.",
"UMask": "0x60"
},
{
"EventName": "fp_pack_ops_retired.fp256_cmp",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point compare ops.",
"UMask": "0x70"
},
{
"EventName": "fp_pack_ops_retired.fp256_cvt",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point convert ops.",
"UMask": "0x80"
},
{
"EventName": "fp_pack_ops_retired.fp256_blend",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point blend ops.",
"UMask": "0x90"
},
{
"EventName": "fp_pack_ops_retired.fp256_shuffle",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "fp_pack_ops_retired.fp256_logical",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point logical ops.",
"UMask": "0xd0"
},
{
"EventName": "fp_pack_ops_retired.fp256_other",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "fp_pack_ops_retired.fp256_all",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "fp_pack_ops_retired.all",
"EventCode": "0x0c",
"BriefDescription": "Retired packed floating-point ops of all types.",
"UMask": "0xff"
},
{
"EventName": "packed_int_op_type.int128_add",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer add ops.",
"UMask": "0x01"
},
{
"EventName": "packed_int_op_type.int128_sub",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer subtract ops.",
"UMask": "0x02"
},
{
"EventName": "packed_int_op_type.int128_mul",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer multiply ops.",
"UMask": "0x03"
},
{
"EventName": "packed_int_op_type.int128_mac",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "packed_int_op_type.int128_aes",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer AES ops.",
"UMask": "0x05"
},
{
"EventName": "packed_int_op_type.int128_sha",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer SHA ops.",
"UMask": "0x06"
},
{
"EventName": "packed_int_op_type.int128_cmp",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer compare ops.",
"UMask": "0x07"
},
{
"EventName": "packed_int_op_type.int128_clm",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer CLM ops.",
"UMask": "0x08"
},
{
"EventName": "packed_int_op_type.int128_shift",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer shift ops.",
"UMask": "0x09"
},
{
"EventName": "packed_int_op_type.int128_mov",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer MOV ops.",
"UMask": "0x0a"
},
{
"EventName": "packed_int_op_type.int128_shuffle",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "packed_int_op_type.int128_pack",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer pack ops.",
"UMask": "0x0c"
},
{
"EventName": "packed_int_op_type.int128_logical",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer logical ops.",
"UMask": "0x0d"
},
{
"EventName": "packed_int_op_type.int128_other",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "packed_int_op_type.int128_all",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "packed_int_op_type.int256_add",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer add ops.",
"UMask": "0x10"
},
{
"EventName": "packed_int_op_type.int256_sub",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer subtract ops.",
"UMask": "0x20"
},
{
"EventName": "packed_int_op_type.int256_mul",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer multiply ops.",
"UMask": "0x30"
},
{
"EventName": "packed_int_op_type.int256_mac",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "packed_int_op_type.int256_cmp",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer compare ops.",
"UMask": "0x70"
},
{
"EventName": "packed_int_op_type.int256_shift",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer shift ops.",
"UMask": "0x90"
},
{
"EventName": "packed_int_op_type.int256_mov",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer MOV ops.",
"UMask": "0xa0"
},
{
"EventName": "packed_int_op_type.int256_shuffle",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "packed_int_op_type.int256_pack",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer pack ops.",
"UMask": "0xc0"
},
{
"EventName": "packed_int_op_type.int256_logical",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer logical ops.",
"UMask": "0xd0"
},
{
"EventName": "packed_int_op_type.int256_other",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "packed_int_op_type.int256_all",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "packed_int_op_type.all",
"EventCode": "0x0d",
"BriefDescription": "Retired packed integer ops of all types.",
"UMask": "0xff"
},
{
"EventName": "fp_disp_faults.x87_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for x87 fills.",
"UMask": "0x01"
},
{
"EventName": "fp_disp_faults.xmm_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for XMM fills.",
"UMask": "0x02"
},
{
"EventName": "fp_disp_faults.ymm_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for YMM fills.",
"UMask": "0x04"
},
{
"EventName": "fp_disp_faults.ymm_spill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for YMM spills.",
"UMask": "0x08"
},
{
"EventName": "fp_disp_faults.sse_avx_all",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults of all types for SSE and AVX ops.",
"UMask": "0x0e"
},
{
"EventName": "fp_disp_faults.all",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults of all types.",
"UMask": "0x0f"
}
]

72
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[
{
"EventName": "ic_cache_fill_l2",
"EventCode": "0x82",
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
},
{
"EventName": "ic_cache_fill_sys",
"EventCode": "0x83",
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache."
},
{
"EventName": "ic_fetch_ibs_events.fetch_tagged",
"EventCode": "0x188",
"BriefDescription": "Fetches tagged by Fetch IBS. Not all tagged fetches result in a valid sample and an IBS interrupt.",
"UMask": "0x02"
},
{
"EventName": "ic_fetch_ibs_events.sample_discarded",
"EventCode": "0x188",
"BriefDescription": "Fetches discarded after being tagged by Fetch IBS due to reasons other than IBS filtering.",
"UMask": "0x04"
},
{
"EventName": "ic_fetch_ibs_events.sample_filtered",
"EventCode": "0x188",
"BriefDescription": "Fetches discarded after being tagged by Fetch IBS due to IBS filtering.",
"UMask": "0x08"
},
{
"EventName": "ic_fetch_ibs_events.sample_valid",
"EventCode": "0x188",
"BriefDescription": "Fetches tagged by Fetch IBS that result in a valid sample and an IBS interrupt.",
"UMask": "0x10"
},
{
"EventName": "ic_tag_hit_miss.instruction_cache_hit",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache hits.",
"UMask": "0x07"
},
{
"EventName": "ic_tag_hit_miss.instruction_cache_miss",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache misses.",
"UMask": "0x18"
},
{
"EventName": "ic_tag_hit_miss.all_instruction_cache_accesses",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache accesses of all types.",
"UMask": "0x1f"
},
{
"EventName": "op_cache_hit_miss.op_cache_hit",
"EventCode": "0x28f",
"BriefDescription": "Op cache hits.",
"UMask": "0x03"
},
{
"EventName": "op_cache_hit_miss.op_cache_miss",
"EventCode": "0x28f",
"BriefDescription": "Op cache misses.",
"UMask": "0x04"
},
{
"EventName": "op_cache_hit_miss.all_op_cache_accesses",
"EventCode": "0x28f",
"BriefDescription": "Op cache accesses of all types.",
"UMask": "0x07"
}
]

266
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[
{
"EventName": "l2_request_g1.group2",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
"UMask": "0x01"
},
{
"EventName": "l2_request_g1.l2_hw_pf",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss).",
"UMask": "0x02"
},
{
"EventName": "l2_request_g1.prefetch_l2_cmd",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: prefetch directly into L2.",
"UMask": "0x04"
},
{
"EventName": "l2_request_g1.cacheable_ic_read",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: instruction cache reads.",
"UMask": "0x10"
},
{
"EventName": "l2_request_g1.ls_rd_blk_c_s",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache shared reads.",
"UMask": "0x20"
},
{
"EventName": "l2_request_g1.rd_blk_x",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache stores.",
"UMask": "0x40"
},
{
"EventName": "l2_request_g1.rd_blk_l",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.",
"UMask": "0x80"
},
{
"EventName": "l2_request_g1.all_dc",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
"UMask": "0xe0"
},
{
"EventName": "l2_request_g1.all_no_prefetch",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of common types not including prefetches.",
"UMask": "0xf1"
},
{
"EventName": "l2_request_g1.all",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of all types.",
"UMask": "0xf7"
},
{
"EventName": "l2_request_g2.ls_rd_sized_nc",
"EventCode": "0x61",
"BriefDescription": "L2 cache requests: non-coherent, non-cacheable LS sized reads.",
"UMask": "0x20"
},
{
"EventName": "l2_request_g2.ls_rd_sized",
"EventCode": "0x61",
"BriefDescription": "L2 cache requests: coherent, non-cacheable LS sized reads.",
"UMask": "0x40"
},
{
"EventName": "l2_wcb_req.wcb_close",
"EventCode": "0x63",
"BriefDescription": "Write Combining Buffer (WCB) closures.",
"UMask": "0x20"
},
{
"EventName": "l2_cache_req_stat.ic_fill_miss",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2.",
"UMask": "0x01"
},
{
"EventName": "l2_cache_req_stat.ic_fill_hit_s",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2.",
"UMask": "0x02"
},
{
"EventName": "l2_cache_req_stat.ic_fill_hit_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2.",
"UMask": "0x04"
},
{
"EventName": "l2_cache_req_stat.ic_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache hits.",
"UMask": "0x06"
},
{
"EventName": "l2_cache_req_stat.ic_access_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache access.",
"UMask": "0x07"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_c",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2.",
"UMask": "0x08"
},
{
"EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses.",
"UMask": "0x09"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2.",
"UMask": "0x10"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2.",
"UMask": "0x20"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2.",
"UMask": "0x40"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_cs",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2.",
"UMask": "0x80"
},
{
"EventName": "l2_cache_req_stat.dc_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
"UMask": "0xf0"
},
{
"EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits.",
"UMask": "0xf6"
},
{
"EventName": "l2_cache_req_stat.dc_access_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
"UMask": "0xf8"
},
{
"EventName": "l2_cache_req_stat.all",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_hit_l2.l2_hwpf",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware prefetchers.",
"UMask": "0x1f"
},
{
"EventName": "l2_pf_hit_l2.l1_dc_hwpf",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data hardware prefetchers.",
"UMask": "0xe0"
},
{
"EventName": "l2_pf_hit_l2.l1_dc_l2_hwpf",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and L2 hardware prefetchers.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_hwpf",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware prefetchers.",
"UMask": "0x1f"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_dc_hwpf",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data hardware prefetchers.",
"UMask": "0xe0"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and L2 hardware prefetchers.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_hwpf",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware prefetchers.",
"UMask": "0x1f"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_dc_hwpf",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data hardware prefetchers.",
"UMask": "0xe0"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_dc_l2_hwpf",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and L2 hardware prefetchers.",
"UMask": "0xff"
},
{
"EventName": "l2_fill_rsp_src.local_ccx",
"EventCode": "0x165",
"BriefDescription": "L2 cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "l2_fill_rsp_src.near_cache",
"EventCode": "0x165",
"BriefDescription": "L2 cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "l2_fill_rsp_src.dram_io_near",
"EventCode": "0x165",
"BriefDescription": "L2 cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "l2_fill_rsp_src.far_cache",
"EventCode": "0x165",
"BriefDescription": "L2 cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "l2_fill_rsp_src.dram_io_far",
"EventCode": "0x165",
"BriefDescription": "L2 cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "l2_fill_rsp_src.alternate_memories",
"EventCode": "0x165",
"BriefDescription": "L2 cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "l2_fill_rsp_src.all",
"EventCode": "0x165",
"BriefDescription": "L2 cache fills from all types of data sources.",
"UMask": "0xde"
}
]

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[
{
"EventName": "l3_lookup_state.l3_miss",
"EventCode": "0x04",
"BriefDescription": "L3 cache misses.",
"UMask": "0x01",
"Unit": "L3PMC"
},
{
"EventName": "l3_lookup_state.l3_hit",
"EventCode": "0x04",
"BriefDescription": "L3 cache hits.",
"UMask": "0xfe",
"Unit": "L3PMC"
},
{
"EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
"EventCode": "0x04",
"BriefDescription": "L3 cache requests for all coherent accesses.",
"UMask": "0xff",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.dram_near",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
"UMask": "0x01",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.dram_far",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
"UMask": "0x02",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.near_cache",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
"UMask": "0x04",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.far_cache",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
"UMask": "0x08",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.ext_near",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
"UMask": "0x10",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.ext_far",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
"UMask": "0x20",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.all",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency from all data sources.",
"UMask": "0x3f",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.dram_near",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
"UMask": "0x01",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.dram_far",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
"UMask": "0x02",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.near_cache",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
"UMask": "0x04",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.far_cache",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
"UMask": "0x08",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.ext_near",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
"UMask": "0x10",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.ext_far",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
"UMask": "0x20",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.all",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from all data sources.",
"UMask": "0x3f",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
}
]

451
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[
{
"EventName": "ls_bad_status2.stli_other",
"EventCode": "0x24",
"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
"UMask": "0x02"
},
{
"EventName": "ls_locks.bus_lock",
"EventCode": "0x25",
"BriefDescription": "Retired Lock instructions which caused a bus lock.",
"UMask": "0x01"
},
{
"EventName": "ls_ret_cl_flush",
"EventCode": "0x26",
"BriefDescription": "Retired CLFLUSH instructions."
},
{
"EventName": "ls_ret_cpuid",
"EventCode": "0x27",
"BriefDescription": "Retired CPUID instructions."
},
{
"EventName": "ls_dispatch.ld_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
"UMask": "0x01"
},
{
"EventName": "ls_dispatch.store_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
"UMask": "0x02"
},
{
"EventName": "ls_dispatch.ld_st_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
"UMask": "0x04"
},
{
"EventName": "ls_dispatch.all",
"EventCode": "0x29",
"BriefDescription": "Number of memory operations dispatched to the load-store unit.",
"UMask": "0x07"
},
{
"EventName": "ls_smi_rx",
"EventCode": "0x2b",
"BriefDescription": "SMIs received."
},
{
"EventName": "ls_int_taken",
"EventCode": "0x2c",
"BriefDescription": "Interrupts taken."
},
{
"EventName": "ls_stlf",
"EventCode": "0x35",
"BriefDescription": "Store-to-load-forward (STLF) hits."
},
{
"EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
"EventCode": "0x37",
"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
"UMask": "0x01"
},
{
"EventName": "ls_mab_alloc.load_store_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.",
"UMask": "0x3f"
},
{
"EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.",
"UMask": "0x40"
},
{
"EventName": "ls_mab_alloc.all_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.",
"UMask": "0x7f"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_l2",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_ccx",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_dmnd_fills_from_sys.near_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_near",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_dmnd_fills_from_sys.far_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_far",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_dmnd_fills_from_sys.alternate_memories",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_dmnd_fills_from_sys.all",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_any_fills_from_sys.local_l2",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_any_fills_from_sys.local_ccx",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_any_fills_from_sys.local_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX.",
"UMask": "0x03"
},
{
"EventName": "ls_any_fills_from_sys.near_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_near",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_any_fills_from_sys.far_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_any_fills_from_sys.remote_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
"UMask": "0x14"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_far",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_any_fills_from_sys.far_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
"UMask": "0x50"
},
{
"EventName": "ls_any_fills_from_sys.all_dram_io",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_any_fills_from_sys.alternate_memories",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_any_fills_from_sys.all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
"UMask": "0x01"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x02"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
"UMask": "0x04"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
"UMask": "0x08"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
"UMask": "0x10"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x20"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
"UMask": "0x40"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
"UMask": "0x80"
},
{
"EventName": "ls_l1_d_tlb_miss.all_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
"UMask": "0xf0"
},
{
"EventName": "ls_l1_d_tlb_miss.all",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses for all page sizes.",
"UMask": "0xff"
},
{
"EventName": "ls_misal_loads.ma64",
"EventCode": "0x47",
"BriefDescription": "64B misaligned (cacheline crossing) loads.",
"UMask": "0x01"
},
{
"EventName": "ls_misal_loads.ma4k",
"EventCode": "0x47",
"BriefDescription": "4kB misaligned (page crossing) loads.",
"UMask": "0x02"
},
{
"EventName": "ls_pref_instr_disp.prefetch",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
"UMask": "0x01"
},
{
"EventName": "ls_pref_instr_disp.prefetch_w",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable).",
"UMask": "0x02"
},
{
"EventName": "ls_pref_instr_disp.prefetch_nta",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
"UMask": "0x04"
},
{
"EventName": "ls_pref_instr_disp.all",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.",
"UMask": "0x07"
},
{
"EventName": "wcb_close.full_line_64b",
"EventCode": "0x50",
"BriefDescription": "Number of events that caused a Write Combining Buffer (WCB) entry to close because all 64 bytes of the entry have been written to.",
"UMask": "0x01"
},
{
"EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
"UMask": "0x01"
},
{
"EventName": "ls_inef_sw_pref.mab_mch_cnt",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB).",
"UMask": "0x02"
},
{
"EventName": "ls_inef_sw_pref.all",
"EventCode": "0x52",
"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core for any reason.",
"UMask": "0x03"
},
{
"EventName": "ls_sw_pf_dc_fills.local_l2",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_sw_pf_dc_fills.local_ccx",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_sw_pf_dc_fills.near_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_near",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_sw_pf_dc_fills.far_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_far",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_sw_pf_dc_fills.alternate_memories",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_sw_pf_dc_fills.all",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_hw_pf_dc_fills.local_l2",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_hw_pf_dc_fills.local_ccx",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_hw_pf_dc_fills.near_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_near",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_hw_pf_dc_fills.far_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_far",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_hw_pf_dc_fills.alternate_memories",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_hw_pf_dc_fills.all",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_alloc_mab_count",
"EventCode": "0x5f",
"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle."
},
{
"EventName": "ls_not_halted_cyc",
"EventCode": "0x76",
"BriefDescription": "Core cycles not in halt."
},
{
"EventName": "ls_tlb_flush.all",
"EventCode": "0x78",
"BriefDescription": "All TLB Flushes.",
"UMask": "0xff"
},
{
"EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",
"EventCode": "0x120",
"BriefDescription": "Reference cycles (P0 frequency) not in halt .",
"UMask": "0x1"
}
]

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[
{
"EventName": "umc_mem_clk",
"PublicDescription": "Number of memory clock (MEMCLK) cycles.",
"EventCode": "0x00",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_act_cmd.all",
"PublicDescription": "Number of ACTIVATE commands sent.",
"EventCode": "0x05",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_act_cmd.rd",
"PublicDescription": "Number of ACTIVATE commands sent for reads.",
"EventCode": "0x05",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_act_cmd.wr",
"PublicDescription": "Number of ACTIVATE commands sent for writes.",
"EventCode": "0x05",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_pchg_cmd.all",
"PublicDescription": "Number of PRECHARGE commands sent.",
"EventCode": "0x06",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_pchg_cmd.rd",
"PublicDescription": "Number of PRECHARGE commands sent for reads.",
"EventCode": "0x06",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_pchg_cmd.wr",
"PublicDescription": "Number of PRECHARGE commands sent for writes.",
"EventCode": "0x06",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_cas_cmd.all",
"PublicDescription": "Number of CAS commands sent.",
"EventCode": "0x0a",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_cas_cmd.rd",
"PublicDescription": "Number of CAS commands sent for reads.",
"EventCode": "0x0a",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_cas_cmd.wr",
"PublicDescription": "Number of CAS commands sent for writes.",
"EventCode": "0x0a",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_data_slot_clks.all",
"PublicDescription": "Number of clock cycles used by the data bus.",
"EventCode": "0x14",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_data_slot_clks.rd",
"PublicDescription": "Number of clock cycles used by the data bus for reads.",
"EventCode": "0x14",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_data_slot_clks.wr",
"PublicDescription": "Number of clock cycles used by the data bus for writes.",
"EventCode": "0x14",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
}
]

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[
{
"MetricName": "total_dispatch_slots",
"BriefDescription": "Total dispatch slots (up to 8 instructions can be dispatched in each cycle).",
"MetricExpr": "8 * ls_not_halted_cyc",
"ScaleUnit": "1slots"
},
{
"MetricName": "frontend_bound",
"BriefDescription": "Percentage of dispatch slots that remained unused because the frontend did not supply enough instructions/ops.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%slots"
},
{
"MetricName": "bad_speculation",
"BriefDescription": "Percentage of dispatched ops that did not retire.",
"MetricExpr": "d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%ops"
},
{
"MetricName": "backend_bound",
"BriefDescription": "Percentage of dispatch slots that remained unused because of backend stalls.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%slots"
},
{
"MetricName": "smt_contention",
"BriefDescription": "Percentage of dispatch slots that remained unused because the other thread was selected.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%slots"
},
{
"MetricName": "retiring",
"BriefDescription": "Percentage of dispatch slots used by ops that retired.",
"MetricExpr": "d_ratio(ex_ret_ops, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%slots"
},
{
"MetricName": "frontend_bound_by_latency",
"BriefDescription": "Percentage of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses).",
"MetricExpr": "d_ratio((8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x8@), total_dispatch_slots)",
"MetricGroup": "PipelineL2;frontend_bound_group",
"ScaleUnit": "100%slots"
},
{
"MetricName": "frontend_bound_by_bandwidth",
"BriefDescription": "Percentage of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth).",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - (8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x8@), total_dispatch_slots)",
"MetricGroup": "PipelineL2;frontend_bound_group",
"ScaleUnit": "100%slots"
},
{
"MetricName": "bad_speculation_from_mispredicts",
"BriefDescription": "Percentage of dispatched ops that were flushed due to branch mispredicts.",
"MetricExpr": "d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + bp_redirects.resync)",
"MetricGroup": "PipelineL2;bad_speculation_group",
"ScaleUnit": "100%ops"
},
{
"MetricName": "bad_speculation_from_pipeline_restarts",
"BriefDescription": "Percentage of dispatched ops that were flushed due to pipeline restarts (resyncs).",
"MetricExpr": "d_ratio(bad_speculation * bp_redirects.resync, ex_ret_brn_misp + bp_redirects.resync)",
"MetricGroup": "PipelineL2;bad_speculation_group",
"ScaleUnit": "100%ops"
},
{
"MetricName": "backend_bound_by_memory",
"BriefDescription": "Percentage of dispatch slots that remained unused because of stalls due to the memory subsystem.",
"MetricExpr": "backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)",
"MetricGroup": "PipelineL2;backend_bound_group",
"ScaleUnit": "100%slots"
},
{
"MetricName": "backend_bound_by_cpu",
"BriefDescription": "Percentage of dispatch slots that remained unused because of stalls not related to the memory subsystem.",
"MetricExpr": "backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))",
"MetricGroup": "PipelineL2;backend_bound_group",
"ScaleUnit": "100%slots"
},
{
"MetricName": "retiring_from_fastpath",
"BriefDescription": "Percentage of dispatch slots used by fastpath ops that retired.",
"MetricExpr": "retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))",
"MetricGroup": "PipelineL2;retiring_group",
"ScaleUnit": "100%slots"
},
{
"MetricName": "retiring_from_microcode",
"BriefDescription": "Percentage of dispatch slots used by microcode ops that retired.",
"MetricExpr": "retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)",
"MetricGroup": "PipelineL2;retiring_group",
"ScaleUnit": "100%slots"
}
]

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[
{
"MetricName": "branch_misprediction_rate",
"BriefDescription": "Execution-time branch misprediction rate (non-speculative).",
"MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
"MetricGroup": "branch_prediction",
"ScaleUnit": "1per_branch"
},
{
"MetricName": "all_data_cache_accesses_pti",
"BriefDescription": "All data cache accesses per thousand instructions.",
"MetricExpr": "ls_dispatch.all / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "all_l2_cache_accesses_pti",
"BriefDescription": "All L2 cache accesses per thousand instructions.",
"MetricExpr": "(l2_request_g1.all_no_prefetch + l2_pf_hit_l2.l2_hwpf + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_accesses_from_l1_ic_misses_pti",
"BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch) per thousand instructions.",
"MetricExpr": "l2_request_g1.cacheable_ic_read / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_accesses_from_l1_dc_misses_pti",
"BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch) per thousand instructions.",
"MetricExpr": "l2_request_g1.all_dc / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_accesses_from_l2_hwpf_pti",
"BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher per thousand instructions.",
"MetricExpr": "(l2_pf_hit_l2.l1_dc_l2_hwpf + l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "all_l2_cache_misses_pti",
"BriefDescription": "All L2 cache misses per thousand instructions.",
"MetricExpr": "(l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_misses_from_l1_ic_miss_pti",
"BriefDescription": "L2 cache misses from L1 instruction cache misses per thousand instructions.",
"MetricExpr": "l2_cache_req_stat.ic_fill_miss / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_misses_from_l1_dc_miss_pti",
"BriefDescription": "L2 cache misses from L1 data cache misses per thousand instructions.",
"MetricExpr": "l2_cache_req_stat.ls_rd_blk_c / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_misses_from_l2_hwpf_pti",
"BriefDescription": "L2 cache misses from L2 cache hardware prefetcher per thousand instructions.",
"MetricExpr": "(l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "all_l2_cache_hits_pti",
"BriefDescription": "All L2 cache hits per thousand instructions.",
"MetricExpr": "(l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.l2_hwpf) / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_hits_from_l1_ic_miss_pti",
"BriefDescription": "L2 cache hits from L1 instruction cache misses per thousand instructions.",
"MetricExpr": "l2_cache_req_stat.ic_hit_in_l2 / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_hits_from_l1_dc_miss_pti",
"BriefDescription": "L2 cache hits from L1 data cache misses per thousand instructions.",
"MetricExpr": "l2_cache_req_stat.dc_hit_in_l2 / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_cache_hits_from_l2_hwpf_pti",
"BriefDescription": "L2 cache hits from L2 cache hardware prefetcher per thousand instructions.",
"MetricExpr": "l2_pf_hit_l2.l1_dc_l2_hwpf / instructions",
"MetricGroup": "l2_cache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l3_cache_accesses",
"BriefDescription": "L3 cache accesses.",
"MetricExpr": "l3_lookup_state.all_coherent_accesses_to_l3",
"MetricGroup": "l3_cache"
},
{
"MetricName": "l3_misses",
"BriefDescription": "L3 misses (including cacheline state change requests).",
"MetricExpr": "l3_lookup_state.l3_miss",
"MetricGroup": "l3_cache"
},
{
"MetricName": "l3_read_miss_latency",
"BriefDescription": "Average L3 read miss latency (in core clocks).",
"MetricExpr": "(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all",
"MetricGroup": "l3_cache",
"ScaleUnit": "1ns"
},
{
"MetricName": "l3_read_miss_latency_for_local_dram",
"BriefDescription": "Average L3 read miss latency (in core clocks) for local DRAM.",
"MetricExpr": "(l3_xi_sampled_latency.dram_near * 10) / l3_xi_sampled_latency_requests.dram_near",
"MetricGroup": "l3_cache",
"ScaleUnit": "1ns"
},
{
"MetricName": "l3_read_miss_latency_for_remote_dram",
"BriefDescription": "Average L3 read miss latency (in core clocks) for remote DRAM.",
"MetricExpr": "(l3_xi_sampled_latency.dram_far * 10) / l3_xi_sampled_latency_requests.dram_far",
"MetricGroup": "l3_cache",
"ScaleUnit": "1ns"
},
{
"MetricName": "op_cache_fetch_miss_ratio",
"BriefDescription": "Op cache miss ratio for all fetches.",
"MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
"ScaleUnit": "100%"
},
{
"MetricName": "ic_fetch_miss_ratio",
"BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit.",
"MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
"ScaleUnit": "100%"
},
{
"MetricName": "l1_data_cache_fills_from_memory_pti",
"BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructions.",
"MetricExpr": "ls_any_fills_from_sys.dram_io_all / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_data_cache_fills_from_remote_node_pti",
"BriefDescription": "L1 data cache fills from a different NUMA node per thousand instructions.",
"MetricExpr": "ls_any_fills_from_sys.far_all / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_data_cache_fills_from_same_ccx_pti",
"BriefDescription": "L1 data cache fills from within the same CCX per thousand instructions.",
"MetricExpr": "ls_any_fills_from_sys.local_all / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_data_cache_fills_from_different_ccx_pti",
"BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node per thousand instructions.",
"MetricExpr": "ls_any_fills_from_sys.remote_cache / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "all_l1_data_cache_fills_pti",
"BriefDescription": "All L1 data cache fills per thousand instructions.",
"MetricExpr": "ls_any_fills_from_sys.all / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_demand_data_cache_fills_from_local_l2_pti",
"BriefDescription": "L1 demand data cache fills from local L2 cache per thousand instructions.",
"MetricExpr": "ls_dmnd_fills_from_sys.local_l2 / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_demand_data_cache_fills_from_same_ccx_pti",
"BriefDescription": "L1 demand data cache fills from within the same CCX per thousand instructions.",
"MetricExpr": "ls_dmnd_fills_from_sys.local_ccx / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_demand_data_cache_fills_from_near_cache_pti",
"BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node per thousand instructions.",
"MetricExpr": "ls_dmnd_fills_from_sys.near_cache / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_demand_data_cache_fills_from_near_memory_pti",
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node per thousand instructions.",
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_near / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_demand_data_cache_fills_from_far_cache_pti",
"BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node per thousand instructions.",
"MetricExpr": "ls_dmnd_fills_from_sys.far_cache / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_demand_data_cache_fills_from_far_memory_pti",
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node per thousand instructions.",
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_far / instructions",
"MetricGroup": "l1_dcache",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_itlb_misses_pti",
"BriefDescription": "L1 instruction TLB misses per thousand instructions.",
"MetricExpr": "(bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all) / instructions",
"MetricGroup": "tlb",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_itlb_misses_pti",
"BriefDescription": "L2 instruction TLB misses and instruction page walks per thousand instructions.",
"MetricExpr": "bp_l1_tlb_miss_l2_tlb_miss.all / instructions",
"MetricGroup": "tlb",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l1_dtlb_misses_pti",
"BriefDescription": "L1 data TLB misses per thousand instructions.",
"MetricExpr": "ls_l1_d_tlb_miss.all / instructions",
"MetricGroup": "tlb",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "l2_dtlb_misses_pti",
"BriefDescription": "L2 data TLB misses and data page walks per thousand instructions.",
"MetricExpr": "ls_l1_d_tlb_miss.all_l2_miss / instructions",
"MetricGroup": "tlb",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "all_tlbs_flushed_pti",
"BriefDescription": "All TLBs flushed per thousand instructions.",
"MetricExpr": "ls_tlb_flush.all / instructions",
"MetricGroup": "tlb",
"ScaleUnit": "1e3per_1k_instr"
},
{
"MetricName": "macro_ops_dispatched",
"BriefDescription": "Macro-ops dispatched.",
"MetricExpr": "de_src_op_disp.all",
"MetricGroup": "decoder"
},
{
"MetricName": "sse_avx_stalls",
"BriefDescription": "Mixed SSE/AVX stalls.",
"MetricExpr": "fp_disp_faults.sse_avx_all"
},
{
"MetricName": "macro_ops_retired",
"BriefDescription": "Macro-ops retired.",
"MetricExpr": "ex_ret_ops"
},
{
"MetricName": "umc_data_bus_utilization",
"BriefDescription": "Memory controller data bus utilization.",
"MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "100%"
},
{
"MetricName": "umc_cas_cmd_rate",
"BriefDescription": "Memory controller CAS command rate.",
"MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1per_memclk"
},
{
"MetricName": "umc_cas_cmd_read_ratio",
"BriefDescription": "Ratio of memory controller CAS commands for reads.",
"MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "100%"
},
{
"MetricName": "umc_cas_cmd_write_ratio",
"BriefDescription": "Ratio of memory controller CAS commands for writes.",
"MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "100%"
},
{
"MetricName": "umc_mem_read_bandwidth",
"BriefDescription": "Estimated memory read bandwidth.",
"MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1MB/s"
},
{
"MetricName": "umc_mem_write_bandwidth",
"BriefDescription": "Estimated memory write bandwidth.",
"MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1MB/s"
},
{
"MetricName": "umc_mem_bandwidth",
"BriefDescription": "Estimated combined memory bandwidth.",
"MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1MB/s"
},
{
"MetricName": "umc_activate_cmd_rate",
"BriefDescription": "Memory controller ACTIVATE command rate.",
"MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1per_memclk"
},
{
"MetricName": "umc_precharge_cmd_rate",
"BriefDescription": "Memory controller PRECHARGE command rate.",
"MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1per_memclk"
}
]

35
tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
View File

@ -732,9 +732,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_data_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "",
@ -745,9 +744,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@ -764,9 +762,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
@ -807,9 +804,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@ -838,16 +834,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_miss_latency",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@ -867,9 +861,8 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_page_walks_utilization",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",

85
tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
View File

@ -670,23 +670,20 @@
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(100 * (1 - tma_core_bound / (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if tma_core_bound < (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
"MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group",
"MetricName": "tma_info_botlnk_core_bound_likely",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Cor;SMT",
"MetricName": "tma_info_botlnk_core_bound_likely"
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + tma_fetch_bandwidth * tma_mite / (tma_mite + tma_dsb)))",
"MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group",
"MetricName": "tma_info_botlnk_dsb_misses",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "DSBmiss;Fed",
"MetricName": "tma_info_botlnk_dsb_misses"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
"MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group",
"MetricName": "tma_info_botlnk_ic_misses",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Fed;FetchLat;IcMiss",
"MetricName": "tma_info_botlnk_ic_misses"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
@ -1045,9 +1042,8 @@
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
"MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_code_stlb_mpki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Fed;MemoryTLB",
"MetricName": "tma_info_memory_code_stlb_mpki"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
@ -1088,9 +1084,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_data_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
@ -1107,9 +1102,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@ -1132,23 +1126,20 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
"MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
"MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_evictions_nonsilent_pki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "L2Evicts;Mem;Server",
"MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
},
{
"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
"MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
"MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_evictions_silent_pki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "L2Evicts;Mem;Server",
"MetricName": "tma_info_memory_l2_evictions_silent_pki"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
@ -1189,9 +1180,8 @@
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_access_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "tma_info_memory_l3_cache_access_bw_2t"
},
{
"BriefDescription": "",
@ -1202,9 +1192,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@ -1233,16 +1222,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_miss_latency",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@ -1253,9 +1240,8 @@
{
"BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_stlb_mpki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_load_stlb_mpki"
},
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
@ -1273,16 +1259,14 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_page_walks_utilization",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_store_stlb_mpki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_store_stlb_mpki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
@ -1313,9 +1297,8 @@
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
"MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
"MetricGroup": "Mem;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_uc_load_pki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem",
"MetricName": "tma_info_memory_uc_load_pki"
},
{
"BriefDescription": "",

10
tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
View File

@ -19,7 +19,7 @@
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
@ -267,11 +267,11 @@
"UMask": "0x4"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
"PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},
@ -321,11 +321,11 @@
"UMask": "0x18"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
"PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
"PublicDescription": "Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
"SampleAfterValue": "2000003",
"UMask": "0x18"
},

2
tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
View File

@ -6866,7 +6866,7 @@
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
"PEBS": "2",
"PublicDescription": "Number of times RTM abort was triggered.",
"SampleAfterValue": "2000003",
"UMask": "0x4"

2
tools/perf/pmu-events/arch/x86/cascadelakex/other.json
View File

@ -19,7 +19,7 @@
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
"UMask": "0x20"
},

2
tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
View File

@ -396,7 +396,7 @@
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
"PEBS": "2",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},

14
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json
View File

@ -38,7 +38,7 @@
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x80",
"Unit": "IRP"
},
@ -47,7 +47,7 @@
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x2",
"Unit": "IRP"
},
@ -56,7 +56,7 @@
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x4",
"Unit": "IRP"
},
@ -65,7 +65,7 @@
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x20",
"Unit": "IRP"
},
@ -74,7 +74,7 @@
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
"PerPkg": "1",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x1",
"Unit": "IRP"
},
@ -101,7 +101,7 @@
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
"PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"PublicDescription": "Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x40",
"Unit": "IRP"
},
@ -500,7 +500,7 @@
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
"PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
"PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
"UMask": "0x2",
"Unit": "IRP"
},

2
tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
View File

@ -205,7 +205,7 @@
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},

2
tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json
View File

@ -267,7 +267,7 @@
"CounterMask": "6",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},

1
tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json
View File

@ -264,6 +264,7 @@
"BriefDescription": "Number of times an RTM execution aborted.",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"

3
tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json
View File

@ -428,6 +428,7 @@
"BriefDescription": "INST_RETIRED.MACRO_FUSED",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.MACRO_FUSED",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
@ -435,6 +436,7 @@
"BriefDescription": "Retired NOP instructions.",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
"PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions",
"SampleAfterValue": "2000003",
"UMask": "0x2"
@ -451,6 +453,7 @@
"BriefDescription": "Iterations of Repeat string retired instructions.",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.REP_ITERATION",
"PEBS": "1",
"PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",
"SampleAfterValue": "2000003",
"UMask": "0x8"

112
tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
View File

@ -4197,6 +4197,42 @@
"UMask": "0xcd43ff04",
"Unit": "CHA"
},
{
"BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd42ff04",
"Unit": "CHA"
},
{
"BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd437f04",
"Unit": "CHA"
},
{
"BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc42ff04",
"Unit": "CHA"
},
{
"BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc437f04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; Misses from local IO",
"EventCode": "0x35",
@ -4207,7 +4243,7 @@
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; ItoM misses from local IO",
"BriefDescription": "TOR Inserts : ItoM, indicating a full cacheline write request, from IO Devices that missed the LLC",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
"PerPkg": "1",
@ -4225,7 +4261,7 @@
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO",
"BriefDescription": "TOR Inserts; RdCur and FsRdCur requests from local IO that miss LLC",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
"PerPkg": "1",
@ -4251,6 +4287,24 @@
"UMask": "0xc8f3ff04",
"Unit": "CHA"
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f2ff04",
"Unit": "CHA"
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f37f04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; RFO from local IO",
"EventCode": "0x35",
@ -5713,6 +5767,42 @@
"UMask": "0xcd43fe04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets local memory",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd42fe04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets remote memory",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd437e04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; ITOM misses from local IO and targets local memory",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc42fe04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; ITOM misses from local IO and targets remote memory",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc437e04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO",
"EventCode": "0x36",
@ -5722,6 +5812,24 @@
"UMask": "0xc8f3fe04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO and targets local memory",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f2fe04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO and targets remote memory",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f37e04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; RFO misses from local IO",
"EventCode": "0x36",

26
tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.json
View File

@ -4888,7 +4888,7 @@
"Unit": "MDF"
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (AD)",
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AD)",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AD",
"PerPkg": "1",
@ -4897,7 +4897,7 @@
"Unit": "MDF"
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (AK)",
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AK)",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AK",
"PerPkg": "1",
@ -4906,7 +4906,7 @@
"Unit": "MDF"
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (AKC)",
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC)",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AKC",
"PerPkg": "1",
@ -4915,7 +4915,7 @@
"Unit": "MDF"
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (BL)",
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (BL)",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.BL",
"PerPkg": "1",
@ -4924,7 +4924,7 @@
"Unit": "MDF"
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (IV)",
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (IV)",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.IV",
"PerPkg": "1",
@ -5291,7 +5291,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
"Unit": "UPI"
},
@ -5300,7 +5300,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
"Unit": "UPI"
},
@ -5309,7 +5309,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
"Unit": "UPI"
},
@ -5318,7 +5318,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
"Unit": "UPI"
},
@ -5763,7 +5763,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
"Unit": "UPI"
},
@ -5772,7 +5772,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
"Unit": "UPI"
},
@ -5781,7 +5781,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
"Unit": "UPI"
},
@ -5790,7 +5790,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
"Unit": "UPI"
},

43
tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
View File

@ -249,10 +249,17 @@
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.ALL_P",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]",
"SampleAfterValue": "1000003"
},
{
@ -284,7 +291,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALL",
"SampleAfterValue": "1000003"
@ -296,6 +303,12 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALL_P",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.",
"EventCode": "0x74",
@ -317,6 +330,13 @@
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb",
"EventCode": "0x74",
@ -325,11 +345,17 @@
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_P]",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ALL",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL]",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ALL_P",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear",
"EventCode": "0x71",
@ -402,12 +428,19 @@
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
"BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.ALL_P]",
"EventCode": "0x72",
"EventName": "TOPDOWN_RETIRING.ALL",
"PEBS": "1",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.ALL]",
"EventCode": "0x72",
"EventName": "TOPDOWN_RETIRING.ALL_P",
"PEBS": "1",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
"EventCode": "0x0e",

28
tools/perf/pmu-events/arch/x86/grandridge/uncore-cache.json
View File

@ -5,7 +5,6 @@
"EventName": "UNC_CHACMS_CLOCKTICKS",
"PerPkg": "1",
"PortMask": "0x000",
"PublicDescription": "UNC_CHACMS_CLOCKTICKS",
"Unit": "CHACMS"
},
{
@ -1216,6 +1215,15 @@
"UMask": "0xc88fff01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
"UMask": "0xc827ff01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache",
"EventCode": "0x36",
@ -1252,6 +1260,15 @@
"UMask": "0xc88ffd01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for Data read opt from local IA that hit the cache",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
"UMask": "0xc827fd01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that hit the cache",
"EventCode": "0x36",
@ -1405,6 +1422,15 @@
"UMask": "0xc88efe01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
"UMask": "0xc827fe01",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache",
"EventCode": "0x36",

35
tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
View File

@ -618,9 +618,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_data_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "",
@ -631,9 +630,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@ -650,9 +648,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
@ -669,9 +666,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@ -700,16 +696,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_miss_latency",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@ -729,9 +723,8 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_page_walks_utilization",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",

2
tools/perf/pmu-events/arch/x86/icelakex/frontend.json
View File

@ -282,7 +282,7 @@
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},

95
tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
View File

@ -667,23 +667,20 @@
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(100 * (1 - max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) / (((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) < (((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
"MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group",
"MetricName": "tma_info_botlnk_core_bound_likely",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Cor;SMT",
"MetricName": "tma_info_botlnk_core_bound_likely"
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
"MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + max(0, topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots - (5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots) * ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2) / ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2 + (IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2)))",
"MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group",
"MetricName": "tma_info_botlnk_dsb_misses",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "DSBmiss;Fed",
"MetricName": "tma_info_botlnk_dsb_misses"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
"MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
"MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group",
"MetricName": "tma_info_botlnk_ic_misses",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Fed;FetchLat;IcMiss",
"MetricName": "tma_info_botlnk_ic_misses"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
@ -1045,16 +1042,14 @@
{
"BriefDescription": "\"Bus lock\" per kilo instruction",
"MetricExpr": "tma_info_memory_mix_bus_lock_pki",
"MetricGroup": "Mem;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_bus_lock_pki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem",
"MetricName": "tma_info_memory_bus_lock_pki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
"MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_code_stlb_mpki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Fed;MemoryTLB",
"MetricName": "tma_info_memory_code_stlb_mpki"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
@ -1095,9 +1090,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_data_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
@ -1114,9 +1108,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@ -1139,23 +1132,20 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
"MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
"MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_evictions_nonsilent_pki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "L2Evicts;Mem;Server",
"MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
},
{
"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
"MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
"MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l2_evictions_silent_pki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "L2Evicts;Mem;Server",
"MetricName": "tma_info_memory_l2_evictions_silent_pki"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
@ -1190,9 +1180,8 @@
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_access_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "tma_info_memory_l3_cache_access_bw_2t"
},
{
"BriefDescription": "",
@ -1203,9 +1192,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@ -1240,23 +1228,20 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_miss_latency",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@",
"MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l2_mlp",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Average Latency for L3 cache miss demand Loads",
"MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_l3_miss_latency",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l3_miss_latency"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@ -1267,9 +1252,8 @@
{
"BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_load_stlb_mpki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_load_stlb_mpki"
},
{
"BriefDescription": "\"Bus lock\" per kilo instruction",
@ -1293,16 +1277,14 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD))",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_page_walks_utilization",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
"MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_store_stlb_mpki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_store_stlb_mpki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
@ -1332,9 +1314,8 @@
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
"MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
"MetricGroup": "Mem;TopdownL1;tma_L1_group",
"MetricName": "tma_info_memory_uc_load_pki",
"MetricgroupNoGroup": "TopdownL1"
"MetricGroup": "Mem",
"MetricName": "tma_info_memory_uc_load_pki"
},
{
"BriefDescription": "",

1
tools/perf/pmu-events/arch/x86/icelakex/memory.json
View File

@ -319,6 +319,7 @@
"BriefDescription": "Number of times an RTM execution aborted.",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"

22
tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json
View File

@ -1580,7 +1580,7 @@
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
"BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE",
@ -1677,7 +1677,7 @@
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
"BriefDescription": "This event is deprecated.",
"Deprecated": "1",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
@ -6782,6 +6782,24 @@
"UMask": "0xc8f3ff04",
"Unit": "CHA"
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices and targets local memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f2ff04",
"Unit": "CHA"
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices and targets remote memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f37f04",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
"EventCode": "0x35",

64
tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json
View File

@ -13523,7 +13523,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
"Unit": "UPI"
},
@ -13532,7 +13532,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
"Unit": "UPI"
},
@ -13541,7 +13541,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
"Unit": "UPI"
},
@ -13550,7 +13550,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
"Unit": "UPI"
},
@ -13559,7 +13559,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x8",
"Unit": "UPI"
},
@ -13568,7 +13568,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x108",
"Unit": "UPI"
},
@ -13577,7 +13577,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x1aa",
"Unit": "UPI"
},
@ -13586,7 +13586,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x12a",
"Unit": "UPI"
},
@ -13595,7 +13595,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xc",
"Unit": "UPI"
},
@ -13604,7 +13604,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10c",
"Unit": "UPI"
},
@ -13613,7 +13613,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xa",
"Unit": "UPI"
},
@ -13622,7 +13622,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10a",
"Unit": "UPI"
},
@ -13631,7 +13631,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x9",
"Unit": "UPI"
},
@ -13640,7 +13640,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x109",
"Unit": "UPI"
},
@ -13649,7 +13649,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xd",
"Unit": "UPI"
},
@ -13658,7 +13658,7 @@
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10d",
"Unit": "UPI"
},
@ -14038,7 +14038,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
"Unit": "UPI"
},
@ -14047,7 +14047,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
"Unit": "UPI"
},
@ -14056,7 +14056,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
"Unit": "UPI"
},
@ -14065,7 +14065,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
"Unit": "UPI"
},
@ -14074,7 +14074,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x8",
"Unit": "UPI"
},
@ -14083,7 +14083,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x108",
"Unit": "UPI"
},
@ -14092,7 +14092,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x1aa",
"Unit": "UPI"
},
@ -14101,7 +14101,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x12a",
"Unit": "UPI"
},
@ -14110,7 +14110,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xc",
"Unit": "UPI"
},
@ -14119,7 +14119,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10c",
"Unit": "UPI"
},
@ -14128,7 +14128,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xa",
"Unit": "UPI"
},
@ -14137,7 +14137,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10a",
"Unit": "UPI"
},
@ -14146,7 +14146,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x9",
"Unit": "UPI"
},
@ -14155,7 +14155,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x109",
"Unit": "UPI"
},
@ -14164,7 +14164,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xd",
"Unit": "UPI"
},
@ -14173,7 +14173,7 @@
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10d",
"Unit": "UPI"
},

11
tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json
View File

@ -2476,17 +2476,6 @@
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "Number requests sent to PCIe from main die : From IRP",
"EventCode": "0xC2",
"EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xFF",
"PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU",
"UMask": "0x1",
"Unit": "IIO"
},
{
"BriefDescription": "Number requests sent to PCIe from main die : From ITC",
"EventCode": "0xC2",

24
tools/perf/pmu-events/arch/x86/lunarlake/cache.json
View File

@ -31,7 +31,7 @@
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x4f",
"Unit": "cpu_atom"
},
@ -94,7 +94,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x400",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -106,7 +106,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -118,7 +118,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -130,7 +130,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x800",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -142,7 +142,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -154,7 +154,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -166,7 +166,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -178,7 +178,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -190,7 +190,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -202,7 +202,7 @@
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
@ -212,7 +212,7 @@
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
"PEBS": "2",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0x6",
"Unit": "cpu_atom"
}

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