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drm/i915: migrate i9xx plane get config
Migrate this code out like the skylake code. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c003bd458a6bcc703e9e2fb05731fb7124012e8c.1612536383.git.jani.nikula@intel.com
This commit is contained in:
parent
12edd6ab14
commit
2a3014490c
3 changed files with 123 additions and 119 deletions
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@ -893,3 +893,122 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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return ERR_PTR(ret);
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}
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static int i9xx_format_to_fourcc(int format)
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{
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switch (format) {
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case DISPPLANE_8BPP:
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return DRM_FORMAT_C8;
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case DISPPLANE_BGRA555:
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return DRM_FORMAT_ARGB1555;
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case DISPPLANE_BGRX555:
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return DRM_FORMAT_XRGB1555;
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case DISPPLANE_BGRX565:
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return DRM_FORMAT_RGB565;
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default:
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case DISPPLANE_BGRX888:
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return DRM_FORMAT_XRGB8888;
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case DISPPLANE_RGBX888:
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return DRM_FORMAT_XBGR8888;
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case DISPPLANE_BGRA888:
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return DRM_FORMAT_ARGB8888;
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case DISPPLANE_RGBA888:
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return DRM_FORMAT_ABGR8888;
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case DISPPLANE_BGRX101010:
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return DRM_FORMAT_XRGB2101010;
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case DISPPLANE_RGBX101010:
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return DRM_FORMAT_XBGR2101010;
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case DISPPLANE_BGRA101010:
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return DRM_FORMAT_ARGB2101010;
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case DISPPLANE_RGBA101010:
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return DRM_FORMAT_ABGR2101010;
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case DISPPLANE_RGBX161616:
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return DRM_FORMAT_XBGR16161616F;
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}
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}
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void
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i9xx_get_initial_plane_config(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_plane *plane = to_intel_plane(crtc->base.primary);
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enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
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enum pipe pipe;
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u32 val, base, offset;
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int fourcc, pixel_format;
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unsigned int aligned_height;
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struct drm_framebuffer *fb;
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struct intel_framebuffer *intel_fb;
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if (!plane->get_hw_state(plane, &pipe))
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return;
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drm_WARN_ON(dev, pipe != crtc->pipe);
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intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
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if (!intel_fb) {
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drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
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return;
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}
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fb = &intel_fb->base;
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fb->dev = dev;
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val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
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if (INTEL_GEN(dev_priv) >= 4) {
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if (val & DISPPLANE_TILED) {
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plane_config->tiling = I915_TILING_X;
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fb->modifier = I915_FORMAT_MOD_X_TILED;
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}
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if (val & DISPPLANE_ROTATE_180)
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plane_config->rotation = DRM_MODE_ROTATE_180;
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}
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if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
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val & DISPPLANE_MIRROR)
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plane_config->rotation |= DRM_MODE_REFLECT_X;
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pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
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fourcc = i9xx_format_to_fourcc(pixel_format);
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fb->format = drm_format_info(fourcc);
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
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base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
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} else if (INTEL_GEN(dev_priv) >= 4) {
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if (plane_config->tiling)
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offset = intel_de_read(dev_priv,
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DSPTILEOFF(i9xx_plane));
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else
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offset = intel_de_read(dev_priv,
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DSPLINOFF(i9xx_plane));
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base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
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} else {
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base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
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}
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plane_config->base = base;
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val = intel_de_read(dev_priv, PIPESRC(pipe));
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fb->width = ((val >> 16) & 0xfff) + 1;
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fb->height = ((val >> 0) & 0xfff) + 1;
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val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
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fb->pitches[0] = val & 0xffffffc0;
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aligned_height = intel_fb_align_height(fb, 0, fb->height);
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plane_config->size = fb->pitches[0] * aligned_height;
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drm_dbg_kms(&dev_priv->drm,
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"%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
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crtc->base.name, plane->base.name, fb->width, fb->height,
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fb->format->cpp[0] * 8, base, fb->pitches[0],
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plane_config->size);
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plane_config->fb = intel_fb;
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}
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@ -10,6 +10,8 @@
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enum pipe;
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struct drm_i915_private;
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struct intel_crtc;
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struct intel_initial_plane_config;
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struct intel_plane;
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struct intel_plane_state;
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@ -21,4 +23,6 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
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struct intel_plane *
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intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe);
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void i9xx_get_initial_plane_config(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config);
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#endif
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@ -2209,39 +2209,6 @@ intel_plane_compute_gtt(struct intel_plane_state *plane_state)
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return intel_plane_check_stride(plane_state);
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}
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static int i9xx_format_to_fourcc(int format)
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{
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switch (format) {
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case DISPPLANE_8BPP:
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return DRM_FORMAT_C8;
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case DISPPLANE_BGRA555:
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return DRM_FORMAT_ARGB1555;
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case DISPPLANE_BGRX555:
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return DRM_FORMAT_XRGB1555;
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case DISPPLANE_BGRX565:
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return DRM_FORMAT_RGB565;
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default:
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case DISPPLANE_BGRX888:
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return DRM_FORMAT_XRGB8888;
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case DISPPLANE_RGBX888:
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return DRM_FORMAT_XBGR8888;
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case DISPPLANE_BGRA888:
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return DRM_FORMAT_ARGB8888;
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case DISPPLANE_RGBA888:
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return DRM_FORMAT_ABGR8888;
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case DISPPLANE_BGRX101010:
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return DRM_FORMAT_XRGB2101010;
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case DISPPLANE_RGBX101010:
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return DRM_FORMAT_XBGR2101010;
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case DISPPLANE_BGRA101010:
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return DRM_FORMAT_ARGB2101010;
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case DISPPLANE_RGBA101010:
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return DRM_FORMAT_ABGR2101010;
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case DISPPLANE_RGBX161616:
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return DRM_FORMAT_XBGR16161616F;
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}
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}
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static struct i915_vma *
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initial_plane_vma(struct drm_i915_private *i915,
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struct intel_initial_plane_config *plane_config)
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@ -5914,92 +5881,6 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
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pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
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}
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static void
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i9xx_get_initial_plane_config(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_plane *plane = to_intel_plane(crtc->base.primary);
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enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
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enum pipe pipe;
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u32 val, base, offset;
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int fourcc, pixel_format;
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unsigned int aligned_height;
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struct drm_framebuffer *fb;
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struct intel_framebuffer *intel_fb;
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if (!plane->get_hw_state(plane, &pipe))
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return;
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drm_WARN_ON(dev, pipe != crtc->pipe);
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intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
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if (!intel_fb) {
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drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
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return;
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}
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fb = &intel_fb->base;
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fb->dev = dev;
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val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
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if (INTEL_GEN(dev_priv) >= 4) {
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if (val & DISPPLANE_TILED) {
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plane_config->tiling = I915_TILING_X;
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fb->modifier = I915_FORMAT_MOD_X_TILED;
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}
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if (val & DISPPLANE_ROTATE_180)
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plane_config->rotation = DRM_MODE_ROTATE_180;
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}
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if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
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val & DISPPLANE_MIRROR)
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plane_config->rotation |= DRM_MODE_REFLECT_X;
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pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
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fourcc = i9xx_format_to_fourcc(pixel_format);
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fb->format = drm_format_info(fourcc);
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
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base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
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} else if (INTEL_GEN(dev_priv) >= 4) {
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if (plane_config->tiling)
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offset = intel_de_read(dev_priv,
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DSPTILEOFF(i9xx_plane));
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else
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offset = intel_de_read(dev_priv,
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DSPLINOFF(i9xx_plane));
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base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
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} else {
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base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
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}
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plane_config->base = base;
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val = intel_de_read(dev_priv, PIPESRC(pipe));
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fb->width = ((val >> 16) & 0xfff) + 1;
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fb->height = ((val >> 0) & 0xfff) + 1;
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val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
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fb->pitches[0] = val & 0xffffffc0;
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aligned_height = intel_fb_align_height(fb, 0, fb->height);
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plane_config->size = fb->pitches[0] * aligned_height;
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drm_dbg_kms(&dev_priv->drm,
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"%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
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crtc->base.name, plane->base.name, fb->width, fb->height,
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fb->format->cpp[0] * 8, base, fb->pitches[0],
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plane_config->size);
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plane_config->fb = intel_fb;
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}
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static void chv_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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