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net: ethernet: mtk_eth_soc: switch to external PCS driver
Now that we got a PCS driver, use it and remove the now redundant PCS code and it's header macros from the Ethernet driver. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Tested-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
4765a9722e
commit
2a3ec7ae31
5 changed files with 56 additions and 319 deletions
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@ -19,6 +19,8 @@ config NET_MEDIATEK_SOC
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select DIMLIB
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select PAGE_POOL
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select PAGE_POOL_STATS
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select PCS_MTK_LYNXI
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select REGMAP_MMIO
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help
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This driver supports the gigabit ethernet MACs in the
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MediaTek SoC family.
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@ -4,7 +4,7 @@
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#
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
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mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
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mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
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mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
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ifdef CONFIG_DEBUG_FS
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mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
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@ -20,6 +20,7 @@
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#include <linux/interrupt.h>
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#include <linux/pinctrl/devinfo.h>
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#include <linux/phylink.h>
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#include <linux/pcs/pcs-mtk-lynxi.h>
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#include <linux/jhash.h>
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#include <linux/bitfield.h>
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#include <net/dsa.h>
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@ -437,7 +438,7 @@ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
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sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
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0 : mac->id;
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return mtk_sgmii_select_pcs(eth->sgmii, sid);
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return eth->sgmii_pcs[sid];
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}
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return NULL;
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@ -4053,8 +4054,17 @@ static int mtk_unreg_dev(struct mtk_eth *eth)
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return 0;
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}
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static void mtk_sgmii_destroy(struct mtk_eth *eth)
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{
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int i;
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for (i = 0; i < MTK_MAX_DEVS; i++)
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mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
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}
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static int mtk_cleanup(struct mtk_eth *eth)
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{
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mtk_sgmii_destroy(eth);
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mtk_unreg_dev(eth);
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mtk_free_dev(eth);
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cancel_work_sync(ð->pending_work);
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@ -4500,6 +4510,36 @@ void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
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rtnl_unlock();
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}
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static int mtk_sgmii_init(struct mtk_eth *eth)
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{
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struct device_node *np;
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struct regmap *regmap;
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u32 flags;
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int i;
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for (i = 0; i < MTK_MAX_DEVS; i++) {
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np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
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if (!np)
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break;
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regmap = syscon_node_to_regmap(np);
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flags = 0;
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if (of_property_read_bool(np, "mediatek,pnswap"))
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flags |= MTK_SGMII_FLAG_PN_SWAP;
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of_node_put(np);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
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eth->soc->ana_rgc3,
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flags);
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}
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return 0;
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}
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static int mtk_probe(struct platform_device *pdev)
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{
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struct resource *res = NULL;
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@ -4563,13 +4603,7 @@ static int mtk_probe(struct platform_device *pdev)
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
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GFP_KERNEL);
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if (!eth->sgmii)
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return -ENOMEM;
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err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
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eth->soc->ana_rgc3);
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err = mtk_sgmii_init(eth);
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if (err)
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return err;
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@ -4580,14 +4614,17 @@ static int mtk_probe(struct platform_device *pdev)
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"mediatek,pctl");
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if (IS_ERR(eth->pctl)) {
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dev_err(&pdev->dev, "no pctl regmap found\n");
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return PTR_ERR(eth->pctl);
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err = PTR_ERR(eth->pctl);
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goto err_destroy_sgmii;
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}
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EINVAL;
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if (!res) {
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err = -EINVAL;
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goto err_destroy_sgmii;
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}
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}
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if (eth->soc->offload_version) {
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@ -4746,6 +4783,8 @@ static int mtk_probe(struct platform_device *pdev)
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mtk_hw_deinit(eth);
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err_wed_exit:
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mtk_wed_exit();
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err_destroy_sgmii:
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mtk_sgmii_destroy(eth);
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return err;
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}
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@ -510,65 +510,6 @@
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#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
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#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
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/* SGMII subsystem config registers */
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/* BMCR (low 16) BMSR (high 16) */
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#define SGMSYS_PCS_CONTROL_1 0x0
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#define SGMII_BMCR GENMASK(15, 0)
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#define SGMII_BMSR GENMASK(31, 16)
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#define SGMII_AN_RESTART BIT(9)
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#define SGMII_ISOLATE BIT(10)
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#define SGMII_AN_ENABLE BIT(12)
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#define SGMII_LINK_STATYS BIT(18)
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#define SGMII_AN_ABILITY BIT(19)
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#define SGMII_AN_COMPLETE BIT(21)
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#define SGMII_PCS_FAULT BIT(23)
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#define SGMII_AN_EXPANSION_CLR BIT(30)
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#define SGMSYS_PCS_ADVERTISE 0x8
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#define SGMII_ADVERTISE GENMASK(15, 0)
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#define SGMII_LPA GENMASK(31, 16)
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/* Register to programmable link timer, the unit in 2 * 8ns */
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#define SGMSYS_PCS_LINK_TIMER 0x18
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#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)
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#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK)
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/* Register to control remote fault */
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#define SGMSYS_SGMII_MODE 0x20
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#define SGMII_IF_MODE_SGMII BIT(0)
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#define SGMII_SPEED_DUPLEX_AN BIT(1)
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#define SGMII_SPEED_MASK GENMASK(3, 2)
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#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
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#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
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#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
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#define SGMII_DUPLEX_HALF BIT(4)
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#define SGMII_IF_MODE_BIT5 BIT(5)
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#define SGMII_REMOTE_FAULT_DIS BIT(8)
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#define SGMII_CODE_SYNC_SET_VAL BIT(9)
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#define SGMII_CODE_SYNC_SET_EN BIT(10)
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#define SGMII_SEND_AN_ERROR_EN BIT(11)
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#define SGMII_IF_MODE_MASK GENMASK(5, 1)
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/* Register to reset SGMII design */
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#define SGMII_RESERVED_0 0x34
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#define SGMII_SW_RESET BIT(0)
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/* Register to set SGMII speed, ANA RG_ Control Signals III*/
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#define SGMSYS_ANA_RG_CS3 0x2028
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#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
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#define RG_PHY_SPEED_1_25G 0x0
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#define RG_PHY_SPEED_3_125G BIT(2)
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/* Register to power up QPHY */
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#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
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#define SGMII_PHYA_PWD BIT(4)
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/* Register to QPHY wrapper control */
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#define SGMSYS_QPHY_WRAP_CTRL 0xec
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#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
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#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
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#define MTK_SGMII_FLAG_PN_SWAP BIT(0)
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/* Infrasys subsystem config registers */
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#define INFRA_MISC2 0x70c
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#define CO_QPHY_SEL BIT(0)
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/* currently no SoC has more than 2 macs */
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#define MTK_MAX_DEVS 2
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/* struct mtk_pcs - This structure holds each sgmii regmap and associated
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* data
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* @regmap: The register map pointing at the range used to setup
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* SGMII modes
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* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
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* @interface: Currently configured interface mode
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* @pcs: Phylink PCS structure
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* @flags: Flags indicating hardware properties
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*/
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struct mtk_pcs {
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struct regmap *regmap;
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u32 ana_rgc3;
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phy_interface_t interface;
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struct phylink_pcs pcs;
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u32 flags;
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};
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/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
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* characteristics
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* @pcs Array of individual PCS structures
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*/
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struct mtk_sgmii {
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struct mtk_pcs pcs[MTK_MAX_DEVS];
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};
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/* struct mtk_eth - This is the main datasructure for holding the state
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* of the driver
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* @dev: The device pointer
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* MII modes
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* @infra: The register map pointing at the range used to setup
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* SGMII and GePHY path
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* @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
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* @pctl: The register map pointing at the range used to setup
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* GMAC port drive/slew values
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* @dma_refcnt: track how many netdevs are using the DMA engine
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u32 msg_enable;
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unsigned long sysclk;
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struct regmap *ethsys;
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struct regmap *infra;
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struct mtk_sgmii *sgmii;
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struct regmap *infra;
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struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
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struct regmap *pctl;
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bool hwlro;
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refcount_t dma_refcnt;
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void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
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u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
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struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id);
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int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
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u32 ana_rgc3);
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int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
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int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
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int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
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@ -1,217 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018-2019 MediaTek Inc.
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/* A library for MediaTek SGMII circuit
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/phylink.h>
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#include <linux/regmap.h>
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#include "mtk_eth_soc.h"
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static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct mtk_pcs, pcs);
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}
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static void mtk_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int bm, adv;
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/* Read the BMSR and LPA */
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
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regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
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phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm),
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FIELD_GET(SGMII_LPA, adv));
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}
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static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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bool mode_changed = false, changed, use_an;
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int rgc3, sgm_mode, bmcr;
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int advertise, link_timer;
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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advertising);
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if (advertise < 0)
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return advertise;
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/* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
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* we assume that fixes it's speed at bitrate = line rate (in
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* other words, 1000Mbps or 2500Mbps).
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*/
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if (interface == PHY_INTERFACE_MODE_SGMII) {
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sgm_mode = SGMII_IF_MODE_SGMII;
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if (phylink_autoneg_inband(mode)) {
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sgm_mode |= SGMII_REMOTE_FAULT_DIS |
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SGMII_SPEED_DUPLEX_AN;
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use_an = true;
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} else {
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use_an = false;
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}
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} else if (phylink_autoneg_inband(mode)) {
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/* 1000base-X or 2500base-X autoneg */
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sgm_mode = SGMII_REMOTE_FAULT_DIS;
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use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
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advertising);
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} else {
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/* 1000base-X or 2500base-X without autoneg */
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sgm_mode = 0;
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use_an = false;
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}
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if (use_an) {
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bmcr = SGMII_AN_ENABLE;
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} else {
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bmcr = 0;
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}
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if (mpcs->interface != interface) {
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link_timer = phylink_get_link_timer_ns(interface);
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if (link_timer < 0)
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return link_timer;
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/* PHYA power down */
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD, SGMII_PHYA_PWD);
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/* Reset SGMII PCS state */
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regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
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SGMII_SW_RESET, SGMII_SW_RESET);
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if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
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SGMII_PN_SWAP_MASK,
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SGMII_PN_SWAP_TX_RX);
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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rgc3 = RG_PHY_SPEED_3_125G;
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else
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rgc3 = 0;
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/* Configure the underlying interface speed */
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regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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RG_PHY_SPEED_3_125G, rgc3);
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/* Setup the link timer */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
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mpcs->interface = interface;
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mode_changed = true;
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}
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/* Update the advertisement, noting whether it has changed */
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regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
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SGMII_ADVERTISE, advertise, &changed);
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/* Update the sgmsys mode register */
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
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SGMII_IF_MODE_SGMII, sgm_mode);
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/* Update the BMCR */
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regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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SGMII_AN_ENABLE, bmcr);
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/* Release PHYA power down state
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* Only removing bit SGMII_PHYA_PWD isn't enough.
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* There are cases when the SGMII_PHYA_PWD register contains 0x9 which
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* prevents SGMII from working. The SGMII still shows link but no traffic
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* can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
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* taken from a good working state of the SGMII interface.
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* Unknown how much the QPHY needs but it is racy without a sleep.
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* Tested on mt7622 & mt7986.
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*/
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usleep_range(50, 100);
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
|
||||
|
||||
return changed || mode_changed;
|
||||
}
|
||||
|
||||
static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
|
||||
{
|
||||
struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
|
||||
|
||||
regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
|
||||
SGMII_AN_RESTART, SGMII_AN_RESTART);
|
||||
}
|
||||
|
||||
static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
|
||||
phy_interface_t interface, int speed, int duplex)
|
||||
{
|
||||
struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
|
||||
unsigned int sgm_mode;
|
||||
|
||||
if (!phylink_autoneg_inband(mode)) {
|
||||
/* Force the speed and duplex setting */
|
||||
if (speed == SPEED_10)
|
||||
sgm_mode = SGMII_SPEED_10;
|
||||
else if (speed == SPEED_100)
|
||||
sgm_mode = SGMII_SPEED_100;
|
||||
else
|
||||
sgm_mode = SGMII_SPEED_1000;
|
||||
|
||||
if (duplex != DUPLEX_FULL)
|
||||
sgm_mode |= SGMII_DUPLEX_HALF;
|
||||
|
||||
regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
|
||||
SGMII_DUPLEX_HALF | SGMII_SPEED_MASK,
|
||||
sgm_mode);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct phylink_pcs_ops mtk_pcs_ops = {
|
||||
.pcs_get_state = mtk_pcs_get_state,
|
||||
.pcs_config = mtk_pcs_config,
|
||||
.pcs_an_restart = mtk_pcs_restart_an,
|
||||
.pcs_link_up = mtk_pcs_link_up,
|
||||
};
|
||||
|
||||
int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
|
||||
{
|
||||
struct device_node *np;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MTK_MAX_DEVS; i++) {
|
||||
np = of_parse_phandle(r, "mediatek,sgmiisys", i);
|
||||
if (!np)
|
||||
break;
|
||||
|
||||
ss->pcs[i].ana_rgc3 = ana_rgc3;
|
||||
ss->pcs[i].regmap = syscon_node_to_regmap(np);
|
||||
|
||||
ss->pcs[i].flags = 0;
|
||||
if (of_property_read_bool(np, "mediatek,pnswap"))
|
||||
ss->pcs[i].flags |= MTK_SGMII_FLAG_PN_SWAP;
|
||||
|
||||
of_node_put(np);
|
||||
if (IS_ERR(ss->pcs[i].regmap))
|
||||
return PTR_ERR(ss->pcs[i].regmap);
|
||||
|
||||
ss->pcs[i].pcs.ops = &mtk_pcs_ops;
|
||||
ss->pcs[i].pcs.poll = true;
|
||||
ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id)
|
||||
{
|
||||
if (!ss->pcs[id].regmap)
|
||||
return NULL;
|
||||
|
||||
return &ss->pcs[id].pcs;
|
||||
}
|
Loading…
Reference in a new issue