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DMAENGINE: ste_dma40: various cosmetic clean-ups
This cleans up some extra newlines, removes some code duplication and moves the code to comply better with checkpatch. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
parent
ff0b12baa5
commit
2a6143407d
2 changed files with 52 additions and 67 deletions
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@ -161,7 +161,8 @@ struct d40_base;
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* @pending_tx: The number of pending transfers. Used between interrupt handler
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* and tasklet.
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* @busy: Set to true when transfer is ongoing on this channel.
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* @phy_chan: Pointer to physical channel which this instance runs on.
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* @phy_chan: Pointer to physical channel which this instance runs on. If this
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* point is NULL, then the channel is not allocated.
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* @chan: DMA engine handle.
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* @tasklet: Tasklet that gets scheduled from interrupt context to complete a
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* transfer and call client callback.
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@ -1236,7 +1237,6 @@ static int d40_free_dma(struct d40_chan *d40c)
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return -EINVAL;
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}
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res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
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if (res) {
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dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
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@ -1305,8 +1305,6 @@ static int d40_free_dma(struct d40_chan *d40c)
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d40c->base->lookup_phy_chans[phy->num] = NULL;
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return 0;
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}
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static int d40_pause(struct dma_chan *chan)
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@ -1314,7 +1312,6 @@ static int d40_pause(struct dma_chan *chan)
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struct d40_chan *d40c =
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container_of(chan, struct d40_chan, chan);
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int res;
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unsigned long flags;
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spin_lock_irqsave(&d40c->lock, flags);
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@ -1510,25 +1507,23 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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struct scatterlist *sgl_dst,
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struct scatterlist *sgl_src,
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unsigned int sgl_len,
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unsigned long flags)
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unsigned long dma_flags)
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{
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int res;
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struct d40_desc *d40d;
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struct d40_chan *d40c = container_of(chan, struct d40_chan,
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chan);
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unsigned long flg;
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unsigned long flags;
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spin_lock_irqsave(&d40c->lock, flg);
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spin_lock_irqsave(&d40c->lock, flags);
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d40d = d40_desc_get(d40c);
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if (d40d == NULL)
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goto err;
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memset(d40d, 0, sizeof(struct d40_desc));
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d40d->lli_len = sgl_len;
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d40d->lli_tx_len = d40d->lli_len;
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d40d->txd.flags = flags;
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d40d->txd.flags = dma_flags;
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if (d40c->log_num != D40_PHY_CHAN) {
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if (d40d->lli_len > d40c->base->plat_data->llis_per_log)
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@ -1556,7 +1551,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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d40d->lli_log.src,
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d40c->log_def.lcsp1,
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d40c->dma_cfg.src_info.data_width,
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flags & DMA_PREP_INTERRUPT,
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dma_flags & DMA_PREP_INTERRUPT,
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d40d->lli_tx_len,
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d40c->base->plat_data->llis_per_log);
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@ -1566,7 +1561,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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d40d->lli_log.dst,
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d40c->log_def.lcsp3,
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d40c->dma_cfg.dst_info.data_width,
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flags & DMA_PREP_INTERRUPT,
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dma_flags & DMA_PREP_INTERRUPT,
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d40d->lli_tx_len,
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d40c->base->plat_data->llis_per_log);
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@ -1612,11 +1607,11 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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d40d->txd.tx_submit = d40_tx_submit;
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spin_unlock_irqrestore(&d40c->lock, flg);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return &d40d->txd;
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err:
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spin_unlock_irqrestore(&d40c->lock, flg);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return NULL;
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}
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EXPORT_SYMBOL(stedma40_memcpy_sg);
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@ -1729,15 +1724,15 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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dma_addr_t dst,
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dma_addr_t src,
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size_t size,
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unsigned long flags)
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unsigned long dma_flags)
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{
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struct d40_desc *d40d;
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struct d40_chan *d40c = container_of(chan, struct d40_chan,
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chan);
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unsigned long flg;
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unsigned long flags;
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int err = 0;
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spin_lock_irqsave(&d40c->lock, flg);
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spin_lock_irqsave(&d40c->lock, flags);
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d40d = d40_desc_get(d40c);
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if (d40d == NULL) {
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@ -1746,9 +1741,7 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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goto err;
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}
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memset(d40d, 0, sizeof(struct d40_desc));
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d40d->txd.flags = flags;
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d40d->txd.flags = dma_flags;
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dma_async_tx_descriptor_init(&d40d->txd, chan);
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@ -1817,7 +1810,7 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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d40d->lli_pool.size, DMA_TO_DEVICE);
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}
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spin_unlock_irqrestore(&d40c->lock, flg);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return &d40d->txd;
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err_fill_lli:
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@ -1825,7 +1818,7 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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"[%s] Failed filling in PHY LLI\n", __func__);
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d40_pool_lli_free(d40d);
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err:
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spin_unlock_irqrestore(&d40c->lock, flg);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return NULL;
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}
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@ -1834,7 +1827,7 @@ static int d40_prep_slave_sg_log(struct d40_desc *d40d,
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struct scatterlist *sgl,
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unsigned int sg_len,
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enum dma_data_direction direction,
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unsigned long flags)
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unsigned long dma_flags)
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{
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dma_addr_t dev_addr = 0;
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int total_size;
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@ -1860,32 +1853,24 @@ static int d40_prep_slave_sg_log(struct d40_desc *d40d,
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if (d40_lcla_id_get(d40c, &d40c->base->lcla_pool) != 0)
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d40d->lli_tx_len = 1;
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if (direction == DMA_FROM_DEVICE) {
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if (direction == DMA_FROM_DEVICE)
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dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
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total_size = d40_log_sg_to_dev(&d40c->lcla,
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sgl, sg_len,
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&d40d->lli_log,
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&d40c->log_def,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width,
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direction,
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flags & DMA_PREP_INTERRUPT,
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dev_addr, d40d->lli_tx_len,
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d40c->base->plat_data->llis_per_log);
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} else if (direction == DMA_TO_DEVICE) {
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else if (direction == DMA_TO_DEVICE)
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dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
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total_size = d40_log_sg_to_dev(&d40c->lcla,
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sgl, sg_len,
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&d40d->lli_log,
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&d40c->log_def,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width,
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direction,
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flags & DMA_PREP_INTERRUPT,
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dev_addr, d40d->lli_tx_len,
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d40c->base->plat_data->llis_per_log);
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} else
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else
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return -EINVAL;
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total_size = d40_log_sg_to_dev(&d40c->lcla,
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sgl, sg_len,
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&d40d->lli_log,
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&d40c->log_def,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width,
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direction,
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dma_flags & DMA_PREP_INTERRUPT,
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dev_addr, d40d->lli_tx_len,
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d40c->base->plat_data->llis_per_log);
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if (total_size < 0)
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return -EINVAL;
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@ -1897,7 +1882,7 @@ static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
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struct scatterlist *sgl,
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unsigned int sgl_len,
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enum dma_data_direction direction,
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unsigned long flags)
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unsigned long dma_flags)
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{
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dma_addr_t src_dev_addr;
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dma_addr_t dst_dev_addr;
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@ -1954,12 +1939,12 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
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struct scatterlist *sgl,
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unsigned int sg_len,
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enum dma_data_direction direction,
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unsigned long flags)
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unsigned long dma_flags)
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{
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struct d40_desc *d40d;
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struct d40_chan *d40c = container_of(chan, struct d40_chan,
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chan);
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unsigned long flg;
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unsigned long flags;
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int err;
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if (d40c->dma_cfg.pre_transfer)
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@ -1967,9 +1952,9 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
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d40c->dma_cfg.pre_transfer_data,
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sg_dma_len(sgl));
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spin_lock_irqsave(&d40c->lock, flg);
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spin_lock_irqsave(&d40c->lock, flags);
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d40d = d40_desc_get(d40c);
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spin_unlock_irqrestore(&d40c->lock, flg);
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spin_unlock_irqrestore(&d40c->lock, flags);
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if (d40d == NULL)
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return NULL;
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@ -1978,10 +1963,10 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
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if (d40c->log_num != D40_PHY_CHAN)
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err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
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direction, flags);
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direction, dma_flags);
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else
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err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
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direction, flags);
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direction, dma_flags);
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if (err) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Failed to prepare %s slave sg job: %d\n",
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@ -1990,7 +1975,7 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
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return NULL;
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}
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d40d->txd.flags = flags;
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d40d->txd.flags = dma_flags;
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dma_async_tx_descriptor_init(&d40d->txd, chan);
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@ -430,25 +430,25 @@ void d40_log_lli_write(struct d40_log_lli_full *lcpa,
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struct d40_log_lli *lli_src,
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int llis_per_log)
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{
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u32 slos = 0;
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u32 dlos = 0;
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u32 slos;
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u32 dlos;
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int i;
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lcpa->lcsp0 = lli_src->lcsp02;
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lcpa->lcsp1 = lli_src->lcsp13;
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lcpa->lcsp2 = lli_dst->lcsp02;
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lcpa->lcsp3 = lli_dst->lcsp13;
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writel(lli_src->lcsp02, &lcpa->lcsp0);
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writel(lli_src->lcsp13, &lcpa->lcsp1);
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writel(lli_dst->lcsp02, &lcpa->lcsp2);
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writel(lli_dst->lcsp13, &lcpa->lcsp3);
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slos = lli_src->lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
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dlos = lli_dst->lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
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for (i = 0; (i < llis_per_log) && slos && dlos; i++) {
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writel(lli_src[i+1].lcsp02, &lcla_src[i].lcsp02);
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writel(lli_src[i+1].lcsp13, &lcla_src[i].lcsp13);
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writel(lli_dst[i+1].lcsp02, &lcla_dst[i].lcsp02);
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writel(lli_dst[i+1].lcsp13, &lcla_dst[i].lcsp13);
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writel(lli_src[i + 1].lcsp02, &lcla_src[i].lcsp02);
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writel(lli_src[i + 1].lcsp13, &lcla_src[i].lcsp13);
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writel(lli_dst[i + 1].lcsp02, &lcla_dst[i].lcsp02);
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writel(lli_dst[i + 1].lcsp13, &lcla_dst[i].lcsp13);
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slos = lli_src[i+1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
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dlos = lli_dst[i+1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
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slos = lli_src[i + 1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
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dlos = lli_dst[i + 1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
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}
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}
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