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ASoC: SOF: Intel: hda: Revisit IMR boot sequence
The sequence for IMR boot is essentially the same as normal boot with the difference that instead of DMA from host the firmware is loaded from IMR. Re-structure the code to use the existing sequence and also add fallback handling in case the IMR boot fails. Introduce a new flag to make the IMR boot support check simpler. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220421202031.1548362-1-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Peter Ujfalusi
Mark Brown
parent
95fa7a62e1
commit
2a68ff8461
3 changed files with 50 additions and 39 deletions
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@ -99,14 +99,14 @@ struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned
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* status on core 1, so power up core 1 also momentarily, keep it in
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* reset/stall and then turn it off
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*/
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static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
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static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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unsigned int status;
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unsigned int status, target_status;
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u32 flags, ipc_hdr, j;
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unsigned long mask;
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char *dump_msg;
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u32 flags, j;
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int ret;
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/* step 1: power up corex */
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@ -119,10 +119,12 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
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hda_ssp_set_cbp_cfp(sdev);
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/* step 2: purge FW request */
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
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chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
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((stream_tag - 1) << 9)));
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/* step 2: Send ROM_CONTROL command (stream_tag is ignored for IMR boot) */
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ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
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if (!imr_boot)
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ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
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/* step 3: unset core 0 reset state & unstall/run core 0 */
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ret = hda_dsp_core_run(sdev, BIT(0));
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@ -169,11 +171,20 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
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/* step 6: enable IPC interrupts */
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hda_dsp_ipc_int_enable(sdev);
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/* step 7: wait for ROM init */
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/*
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* step 7:
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* - Cold/Full boot: wait for ROM init to proceed to download the firmware
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* - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)
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*/
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if (imr_boot)
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target_status = HDA_DSP_ROM_FW_ENTERED;
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else
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target_status = HDA_DSP_ROM_INIT;
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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chip->rom_status_reg, status,
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((status & HDA_DSP_ROM_STS_MASK)
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== HDA_DSP_ROM_INIT),
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== target_status),
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HDA_DSP_REG_POLL_INTERVAL_US,
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chip->rom_init_timeout *
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USEC_PER_MSEC);
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@ -358,32 +369,11 @@ int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
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static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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unsigned long mask;
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u32 j;
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int ret;
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/* power up & unstall/run the cores to run the firmware */
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ret = hda_dsp_enable_core(sdev, chip->init_core_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "dsp core start failed %d\n", ret);
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return -EIO;
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}
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/* set enabled cores mask and increment ref count for cores in init_core_mask */
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sdev->enabled_cores_mask |= chip->init_core_mask;
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mask = sdev->enabled_cores_mask;
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for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES)
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sdev->dsp_core_ref_count[j]++;
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hda_ssp_set_cbp_cfp(sdev);
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/* enable IPC interrupts */
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hda_dsp_ipc_int_enable(sdev);
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/* process wakes */
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hda_sdw_process_wakeen(sdev);
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ret = cl_dsp_init(sdev, 0, true);
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if (ret >= 0)
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hda_sdw_process_wakeen(sdev);
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return ret;
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}
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@ -399,11 +389,14 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
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struct snd_dma_buffer dmab;
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int ret, ret1, i;
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if ((sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT) &&
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!(sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) &&
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!sdev->first_boot) {
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if (hda->imrboot_supported && !sdev->first_boot) {
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dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n");
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return hda_dsp_boot_imr(sdev);
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hda->boot_iteration = 0;
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ret = hda_dsp_boot_imr(sdev);
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if (ret >= 0)
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return ret;
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dev_warn(sdev->dev, "IMR restore failed, trying to cold boot\n");
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}
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chip_info = desc->chip_info;
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@ -437,7 +430,7 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
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"Attempting iteration %d of Core En/ROM load...\n", i);
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hda->boot_iteration = i + 1;
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ret = cl_dsp_init(sdev, hext_stream->hstream.stream_tag);
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ret = cl_dsp_init(sdev, hext_stream->hstream.stream_tag, false);
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/* don't retry anymore if successful */
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if (!ret)
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@ -525,12 +518,19 @@ int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
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int ret;
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if (sdev->first_boot) {
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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ret = hda_sdw_startup(sdev);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: could not startup SoundWire links\n");
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return ret;
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}
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/* Check if IMR boot is usable */
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
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sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT)
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hdev->imrboot_supported = true;
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}
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hda_sdw_int_enable(sdev, true);
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@ -210,7 +210,9 @@
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#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
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#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
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#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
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#define HDA_DSP_IPC_PURGE_FW 0x01004000
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#define HDA_DSP_ROM_IPC_CONTROL 0x01000000
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#define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000
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/* various timeout values */
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#define HDA_DSP_PU_TIMEOUT 50
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@ -416,6 +418,8 @@ enum sof_hda_D0_substate {
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/* represents DSP HDA controller frontend - i.e. host facing control */
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struct sof_intel_hda_dev {
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bool imrboot_supported;
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int boot_iteration;
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struct hda_bus hbus;
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@ -56,11 +56,18 @@ static int icl_dsp_post_fw_run(struct snd_sof_dev *sdev)
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int ret;
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if (sdev->first_boot) {
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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ret = hda_sdw_startup(sdev);
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if (ret < 0) {
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dev_err(sdev->dev, "error: could not startup SoundWire links\n");
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return ret;
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}
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/* Check if IMR boot is usable */
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
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sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT)
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hdev->imrboot_supported = true;
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}
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hda_sdw_int_enable(sdev, true);
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