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perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support

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M3 Intel UPI is the interface between the mesh and the Intel UPI link
layer. It is responsible for translating between the mesh protocol
packets and the flits that are used for transmitting data across the
Intel UPI interface.

The layout of the control registers for a M3UPI uncore unit is similar
to a UPI uncore unit.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-11-git-send-email-kan.liang@linux.intel.com
This commit is contained in:
Kan Liang 2021-06-30 14:08:34 -07:00 committed by Peter Zijlstra
parent da5a9156cd
commit 2a8e51eae7
1 changed files with 6 additions and 1 deletions
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7
arch/x86/events/intel/uncore_snbep.c
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@ -5703,6 +5703,11 @@ static struct intel_uncore_type spr_uncore_upi = {
.name = "upi",
};
static struct intel_uncore_type spr_uncore_m3upi = {
SPR_UNCORE_PCI_COMMON_FORMAT(),
.name = "m3upi",
};
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@ -5715,7 +5720,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_imc,
&spr_uncore_m2m,
&spr_uncore_upi,
NULL,
&spr_uncore_m3upi,
NULL,
NULL,
};