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dt-bindings: clock: samsung: convert Exynos5260 to dtschema
Convert Samsung Exynos5260 SoC clock controller bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220102115356.75796-6-krzysztof.kozlowski@canonical.com
This commit is contained in:
Krzysztof Kozlowski
Rob Herring
parent
c47db13bdf
commit
2ae8dab876
2 changed files with 382 additions and 190 deletions
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@ -1,190 +0,0 @@
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* Samsung Exynos5260 Clock Controller
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Exynos5260 has 13 clock controllers which are instantiated
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independently from the device-tree. These clock controllers
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generate and supply clocks to various hardware blocks within
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the SoC.
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Each clock is assigned an identifier and client nodes can use
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this identifier to specify the clock which they consume. All
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available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos5260-clk.h header and can be used in
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device tree sources.
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External clocks:
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There are several clocks that are generated outside the SoC. It
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is expected that they are defined using standard clock bindings
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with following clock-output-names:
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- "fin_pll" - PLL input clock from XXTI
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- "xrtcxti" - input clock from XRTCXTI
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- "ioclk_pcm_extclk" - pcm external operation clock
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- "ioclk_spdif_extclk" - spdif external operation clock
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- "ioclk_i2s_cdclk" - i2s0 codec clock
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Phy clocks:
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There are several clocks which are generated by specific PHYs.
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These clocks are fed into the clock controller and then routed to
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the hardware blocks. These clocks are defined as fixed clocks in the
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driver with following names:
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- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
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- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
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- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
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- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
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- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
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- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
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- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
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- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
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- "phyclk_dptx_phy_clk_div2"
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- "phyclk_mipi_dphy_4l_m_rxclkesc0"
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- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
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- "phyclk_usbhost20_phy_freeclk"
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- "phyclk_usbhost20_phy_clk48mohci"
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- "phyclk_usbdrd30_udrd30_pipe_pclk"
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- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
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Required Properties for Clock Controller:
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- compatible: should be one of the following.
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1) "samsung,exynos5260-clock-top"
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2) "samsung,exynos5260-clock-peri"
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3) "samsung,exynos5260-clock-egl"
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4) "samsung,exynos5260-clock-kfc"
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5) "samsung,exynos5260-clock-g2d"
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6) "samsung,exynos5260-clock-mif"
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7) "samsung,exynos5260-clock-mfc"
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8) "samsung,exynos5260-clock-g3d"
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9) "samsung,exynos5260-clock-fsys"
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10) "samsung,exynos5260-clock-aud"
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11) "samsung,exynos5260-clock-isp"
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12) "samsung,exynos5260-clock-gscl"
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13) "samsung,exynos5260-clock-disp"
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- reg: physical base address of the controller and the length of
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memory mapped region.
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- #clock-cells: should be 1.
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- clocks: list of clock identifiers which are fed as the input to
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the given clock controller. Please refer the next section to find
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the input clocks for a given controller.
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- clock-names: list of names of clocks which are fed as the input
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to the given clock controller.
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Input clocks for top clock controller:
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- fin_pll
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- dout_mem_pll
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- dout_bus_pll
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- dout_media_pll
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Input clocks for peri clock controller:
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- fin_pll
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- ioclk_pcm_extclk
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- ioclk_i2s_cdclk
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- ioclk_spdif_extclk
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- phyclk_hdmi_phy_ref_cko
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- dout_aclk_peri_66
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- dout_sclk_peri_uart0
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- dout_sclk_peri_uart1
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- dout_sclk_peri_uart2
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- dout_sclk_peri_spi0_b
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- dout_sclk_peri_spi1_b
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- dout_sclk_peri_spi2_b
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- dout_aclk_peri_aud
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- dout_sclk_peri_spi0_b
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Input clocks for egl clock controller:
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- fin_pll
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- dout_bus_pll
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Input clocks for kfc clock controller:
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- fin_pll
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- dout_media_pll
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Input clocks for g2d clock controller:
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- fin_pll
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- dout_aclk_g2d_333
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Input clocks for mif clock controller:
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- fin_pll
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Input clocks for mfc clock controller:
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- fin_pll
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- dout_aclk_mfc_333
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Input clocks for g3d clock controller:
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- fin_pll
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Input clocks for fsys clock controller:
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- fin_pll
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- phyclk_usbhost20_phy_phyclock
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- phyclk_usbhost20_phy_freeclk
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- phyclk_usbhost20_phy_clk48mohci
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- phyclk_usbdrd30_udrd30_pipe_pclk
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- phyclk_usbdrd30_udrd30_phyclock
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- dout_aclk_fsys_200
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Input clocks for aud clock controller:
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- fin_pll
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- fout_aud_pll
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- ioclk_i2s_cdclk
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- ioclk_pcm_extclk
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Input clocks for isp clock controller:
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- fin_pll
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- dout_aclk_isp1_266
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- dout_aclk_isp1_400
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- mout_aclk_isp1_266
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Input clocks for gscl clock controller:
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- fin_pll
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- dout_aclk_gscl_400
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- dout_aclk_gscl_333
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Input clocks for disp clock controller:
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- fin_pll
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- phyclk_dptx_phy_ch3_txd_clk
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- phyclk_dptx_phy_ch2_txd_clk
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- phyclk_dptx_phy_ch1_txd_clk
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- phyclk_dptx_phy_ch0_txd_clk
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- phyclk_hdmi_phy_tmds_clko
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- phyclk_hdmi_phy_ref_clko
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- phyclk_hdmi_phy_pixel_clko
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- phyclk_hdmi_link_o_tmds_clkhi
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- phyclk_mipi_dphy_4l_m_txbyte_clkhs
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- phyclk_dptx_phy_o_ref_clk_24m
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- phyclk_dptx_phy_clk_div2
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- phyclk_mipi_dphy_4l_m_rxclkesc0
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- phyclk_hdmi_phy_ref_cko
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- ioclk_spdif_extclk
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- dout_aclk_peri_aud
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- dout_aclk_disp_222
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- dout_sclk_disp_pixel
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- dout_aclk_disp_333
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Example 1: An example of a clock controller node is listed below.
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clock_mfc: clock-controller@11090000 {
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compatible = "samsung,exynos5260-clock-mfc";
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clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
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clock-names = "fin_pll", "dout_aclk_mfc_333";
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reg = <0x11090000 0x10000>;
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#clock-cells = <1>;
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};
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Example 2: UART controller node that consumes the clock generated by the
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peri clock controller. Refer to the standard clock bindings for
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information about 'clocks' and 'clock-names' property.
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serial@12c00000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <0 146 0>;
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clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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};
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@ -0,0 +1,382 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos5260 SoC clock controller
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maintainers:
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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name::
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- "fin_pll" - PLL input clock from XXTI
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- "xrtcxti" - input clock from XRTCXTI
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- "ioclk_pcm_extclk" - pcm external operation clock
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- "ioclk_spdif_extclk" - spdif external operation clock
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- "ioclk_i2s_cdclk" - i2s0 codec clock
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Phy clocks::
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There are several clocks which are generated by specific PHYs. These clocks
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are fed into the clock controller and then routed to the hardware blocks.
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These clocks are defined as fixed clocks in the driver with following names::
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- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
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- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
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- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
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- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
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- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
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- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
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- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
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- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
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- "phyclk_dptx_phy_clk_div2"
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- "phyclk_mipi_dphy_4l_m_rxclkesc0"
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- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
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- "phyclk_usbhost20_phy_freeclk"
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- "phyclk_usbhost20_phy_clk48mohci"
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- "phyclk_usbdrd30_udrd30_pipe_pclk"
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- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/exynos5260-clk.h header.
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properties:
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compatible:
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enum:
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- samsung,exynos5260-clock-top
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- samsung,exynos5260-clock-peri
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- samsung,exynos5260-clock-egl
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- samsung,exynos5260-clock-kfc
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- samsung,exynos5260-clock-g2d
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- samsung,exynos5260-clock-mif
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- samsung,exynos5260-clock-mfc
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- samsung,exynos5260-clock-g3d
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- samsung,exynos5260-clock-fsys
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- samsung,exynos5260-clock-aud
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- samsung,exynos5260-clock-isp
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- samsung,exynos5260-clock-gscl
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- samsung,exynos5260-clock-disp
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clocks:
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minItems: 1
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maxItems: 19
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clock-names:
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minItems: 1
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maxItems: 19
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- "#clock-cells"
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-top
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: fin_pll
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- const: dout_mem_pll
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- const: dout_bus_pll
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- const: dout_media_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-peri
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then:
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properties:
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: fin_pll
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- const: ioclk_pcm_extclk
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- const: ioclk_i2s_cdclk
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- const: ioclk_spdif_extclk
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- const: phyclk_hdmi_phy_ref_cko
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- const: dout_aclk_peri_66
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- const: dout_sclk_peri_uart0
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- const: dout_sclk_peri_uart1
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- const: dout_sclk_peri_uart2
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- const: dout_sclk_peri_spi0_b
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- const: dout_sclk_peri_spi1_b
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- const: dout_sclk_peri_spi2_b
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- const: dout_aclk_peri_aud
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-egl
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_bus_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-kfc
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_media_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-g2d
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_g2d_333
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-mif
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 1
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clock-names:
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items:
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- const: fin_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-mfc
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_mfc_333
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-g3d
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 1
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clock-names:
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items:
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- const: fin_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5260-clock-fsys
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: fin_pll
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- const: phyclk_usbhost20_phy_phyclock
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- const: phyclk_usbhost20_phy_freeclk
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- const: phyclk_usbhost20_phy_clk48mohci
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- const: phyclk_usbdrd30_udrd30_pipe_pclk
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- const: phyclk_usbdrd30_udrd30_phyclock
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- const: dout_aclk_fsys_200
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
|
||||
const: samsung,exynos5260-clock-aud
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: fout_aud_pll
|
||||
- const: ioclk_i2s_cdclk
|
||||
- const: ioclk_pcm_extclk
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-isp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_isp1_266
|
||||
- const: dout_aclk_isp1_400
|
||||
- const: mout_aclk_isp1_266
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-gscl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_aclk_gscl_400
|
||||
- const: dout_aclk_gscl_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5260-clock-disp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 19
|
||||
maxItems: 19
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: phyclk_dptx_phy_ch3_txd_clk
|
||||
- const: phyclk_dptx_phy_ch2_txd_clk
|
||||
- const: phyclk_dptx_phy_ch1_txd_clk
|
||||
- const: phyclk_dptx_phy_ch0_txd_clk
|
||||
- const: phyclk_hdmi_phy_tmds_clko
|
||||
- const: phyclk_hdmi_phy_ref_clko
|
||||
- const: phyclk_hdmi_phy_pixel_clko
|
||||
- const: phyclk_hdmi_link_o_tmds_clkhi
|
||||
- const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
|
||||
- const: phyclk_dptx_phy_o_ref_clk_24m
|
||||
- const: phyclk_dptx_phy_clk_div2
|
||||
- const: phyclk_mipi_dphy_4l_m_rxclkesc0
|
||||
- const: phyclk_hdmi_phy_ref_cko
|
||||
- const: ioclk_spdif_extclk
|
||||
- const: dout_aclk_peri_aud
|
||||
- const: dout_aclk_disp_222
|
||||
- const: dout_sclk_disp_pixel
|
||||
- const: dout_aclk_disp_333
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5260-clk.h>
|
||||
|
||||
fin_pll: clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "fin_pll";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clock-controller@10010000 {
|
||||
compatible = "samsung,exynos5260-clock-top";
|
||||
reg = <0x10010000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_mif MIF_DOUT_MEM_PLL>,
|
||||
<&clock_mif MIF_DOUT_BUS_PLL>,
|
||||
<&clock_mif MIF_DOUT_MEDIA_PLL>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_mem_pll",
|
||||
"dout_bus_pll",
|
||||
"dout_media_pll";
|
||||
};
|
||||
Loading…
Reference in a new issue