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phy: miphy28lp: Add SSC support for SATA
This patch to tune on/off the ssc on miphy sata setup. User can now enable ssc via dt blob, it is useful to reduce effects of EMI. Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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2 changed files with 47 additions and 0 deletions
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@ -39,6 +39,7 @@ Optional properties (port (child) node):
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register.
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- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
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line).
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- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
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example:
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@ -191,6 +191,8 @@
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#define SYSCFG_PCIE_PCIE_VAL 0x80
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#define SATA_SPDMODE 1
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#define MIPHY_SATA_BANK_NB 3
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struct miphy28lp_phy {
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struct phy *phy;
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struct miphy28lp_dev *phydev;
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@ -200,6 +202,7 @@ struct miphy28lp_phy {
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bool osc_force_ext;
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bool osc_rdy;
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bool px_rx_pol_inv;
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bool ssc;
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struct reset_control *miphy_rst;
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@ -550,6 +553,44 @@ static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy)
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writeb_relaxed(0x00, base + MIPHY_CONF);
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}
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static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
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{
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void __iomem *base = miphy_phy->base;
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u8 val;
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/* Compensate Tx impedance to avoid out of range values */
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/*
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* Enable the SSC on PLL for all banks
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* SSC Modulation @ 31 KHz and 4000 ppm modulation amp
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*/
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val = readb_relaxed(base + MIPHY_BOUNDARY_2);
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val |= SSC_EN_SW;
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writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
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val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
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val |= SSC_SEL;
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writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
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for (val = 0; val < MIPHY_SATA_BANK_NB; val++) {
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writeb_relaxed(val, base + MIPHY_CONF);
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/* Add value to each reference clock cycle */
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/* and define the period length of the SSC */
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writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
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writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
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writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
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/* Clear any previous request */
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writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
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/* requests the PLL to take in account new parameters */
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writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
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/* To be sure there is no other pending requests */
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writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
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}
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}
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static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
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{
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void __iomem *base = miphy_phy->base;
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@ -585,6 +626,9 @@ static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
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writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
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}
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if (miphy_phy->ssc)
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miphy_sata_tune_ssc(miphy_phy);
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return 0;
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}
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@ -1064,6 +1108,8 @@ static int miphy28lp_of_probe(struct device_node *np,
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miphy_phy->px_rx_pol_inv =
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of_property_read_bool(np, "st,px_rx_pol_inv");
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miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
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of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
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if (!miphy_phy->sata_gen)
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miphy_phy->sata_gen = SATA_GEN1;
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