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spi: imx: drop unnecessary read/modify/write
When the MX51_ECSPI_DMA is configured we control every single bit of the register, so there's no need to read/modify/write it. Instead just write the value we want to have in the register. Also, drop unnecessary check if we are actually doing DMA. The values written to the register have no effect in PIO mode and value written there during the last DMA transfer is still in the register, so we can equally well always write a value. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
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parent
c008a80071
commit
2b0fd069ec
1 changed files with 9 additions and 20 deletions
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@ -240,9 +240,9 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
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#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
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#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
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#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
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#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
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#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
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#define MX51_ECSPI_DMA_TEDEN (1 << 7)
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#define MX51_ECSPI_DMA_RXDEN (1 << 23)
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#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
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#define MX51_ECSPI_STAT 0x18
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#define MX51_ECSPI_STAT_RR (1 << 3)
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@ -318,8 +318,7 @@ static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
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u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
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u32 clk = config->speed_hz, delay, reg;
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/*
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@ -392,22 +391,12 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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* Configure the DMA register: setup the watermark
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* and enable DMA request.
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*/
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if (spi_imx->dma_is_inited) {
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dma = readl(spi_imx->base + MX51_ECSPI_DMA);
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rx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
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tx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
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rxt_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
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dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
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& ~MX51_ECSPI_DMA_RX_WML_MASK
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& ~MX51_ECSPI_DMA_RXT_WML_MASK)
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| rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
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|(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
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|(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
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|(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
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writel(dma, spi_imx->base + MX51_ECSPI_DMA);
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}
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writel(spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET |
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spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET |
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spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET |
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MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
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MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
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return 0;
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}
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