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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-30 14:19:16 +00:00
x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detection
Need this in the next patch in time_init and that happens early. This includes a minor fix on i386 where early_intel_workarounds() [which is now called early_init_intel] really executes early as the comments say. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
parent
68071a9665
commit
2b16a23538
5 changed files with 59 additions and 24 deletions
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@ -63,6 +63,15 @@ static __cpuinit int amd_apic_timer_broken(void)
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int force_mwait __cpuinitdata;
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int force_mwait __cpuinitdata;
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void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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{
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if (cpuid_eax(0x80000000) >= 0x80000007) {
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c->x86_power = cpuid_edx(0x80000007);
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if (c->x86_power & (1<<8))
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set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
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}
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}
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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{
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u32 l, h;
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u32 l, h;
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@ -85,6 +94,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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}
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}
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#endif
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#endif
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early_init_amd(c);
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/*
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/*
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* FIXME: We should handle the K5 here. Set up the write
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* FIXME: We should handle the K5 here. Set up the write
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* range and also turn on MSR 83 bits 4 and 31 (write alloc,
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* range and also turn on MSR 83 bits 4 and 31 (write alloc,
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@ -257,12 +268,6 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
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c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
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}
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}
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if (cpuid_eax(0x80000000) >= 0x80000007) {
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c->x86_power = cpuid_edx(0x80000007);
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if (c->x86_power & (1<<8))
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set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
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}
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#ifdef CONFIG_X86_HT
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#ifdef CONFIG_X86_HT
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/*
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/*
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* On a AMD multi core setup the lower bits of the APIC id
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* On a AMD multi core setup the lower bits of the APIC id
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@ -307,6 +307,15 @@ static void __init early_cpu_detect(void)
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cpu_detect(c);
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cpu_detect(c);
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get_cpu_vendor(c, 1);
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get_cpu_vendor(c, 1);
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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early_init_amd(c);
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break;
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case X86_VENDOR_INTEL:
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early_init_intel(c);
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break;
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}
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}
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}
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static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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@ -364,8 +373,6 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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init_scattered_cpuid_features(c);
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init_scattered_cpuid_features(c);
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}
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}
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early_intel_workaround(c);
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#ifdef CONFIG_X86_HT
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#ifdef CONFIG_X86_HT
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c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
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c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
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#endif
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#endif
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@ -24,5 +24,6 @@ extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
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extern int get_model_name(struct cpuinfo_x86 *c);
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extern int get_model_name(struct cpuinfo_x86 *c);
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extern void display_cacheinfo(struct cpuinfo_x86 *c);
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extern void display_cacheinfo(struct cpuinfo_x86 *c);
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extern void early_intel_workaround(struct cpuinfo_x86 *c);
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extern void early_init_intel(struct cpuinfo_x86 *c);
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extern void early_init_amd(struct cpuinfo_x86 *c);
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@ -29,13 +29,14 @@
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struct movsl_mask movsl_mask __read_mostly;
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struct movsl_mask movsl_mask __read_mostly;
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#endif
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#endif
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void __cpuinit early_intel_workaround(struct cpuinfo_x86 *c)
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void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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{
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{
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if (c->x86_vendor != X86_VENDOR_INTEL)
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return;
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/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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if (c->x86 == 15 && c->x86_cache_alignment == 64)
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if (c->x86 == 15 && c->x86_cache_alignment == 64)
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c->x86_cache_alignment = 128;
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c->x86_cache_alignment = 128;
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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}
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}
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/*
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/*
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@ -115,6 +116,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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unsigned int l2 = 0;
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unsigned int l2 = 0;
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char *p = NULL;
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char *p = NULL;
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early_init_intel(c);
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#ifdef CONFIG_X86_F00F_BUG
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#ifdef CONFIG_X86_F00F_BUG
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/*
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/*
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* All current models of Pentium and Pentium with MMX technology CPUs
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* All current models of Pentium and Pentium with MMX technology CPUs
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@ -210,10 +213,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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}
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}
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if (c->x86 == 6)
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if (c->x86 == 6)
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set_bit(X86_FEATURE_P3, c->x86_capability);
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set_bit(X86_FEATURE_P3, c->x86_capability);
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
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if (cpu_has_ds) {
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if (cpu_has_ds) {
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unsigned int l1;
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unsigned int l1;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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@ -544,9 +544,6 @@ static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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c->x86_cache_size, ecx & 0xFF);
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c->x86_cache_size, ecx & 0xFF);
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}
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}
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if (n >= 0x80000007)
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cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
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if (n >= 0x80000008) {
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if (n >= 0x80000008) {
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cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
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cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
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c->x86_virt_bits = (eax >> 8) & 0xff;
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c->x86_virt_bits = (eax >> 8) & 0xff;
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@ -624,7 +621,7 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
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#endif
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#endif
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}
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}
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static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
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{
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{
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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unsigned bits, ecx;
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unsigned bits, ecx;
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@ -682,6 +679,15 @@ static __cpuinit int amd_apic_timer_broken(void)
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return 0;
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return 0;
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}
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}
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static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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{
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early_init_amd_mc(c);
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/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
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if (c->x86_power & (1<<8))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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}
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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{
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unsigned level;
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unsigned level;
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@ -731,10 +737,6 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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}
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}
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display_cacheinfo(c);
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display_cacheinfo(c);
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/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
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if (c->x86_power & (1<<8))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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/* Multi core CPU? */
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/* Multi core CPU? */
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if (c->extended_cpuid_level >= 0x80000008)
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if (c->extended_cpuid_level >= 0x80000008)
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amd_detect_cmp(c);
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amd_detect_cmp(c);
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@ -845,6 +847,13 @@ static void srat_detect_node(void)
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#endif
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#endif
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}
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}
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static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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{
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
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}
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static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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{
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{
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/* Cache sizes */
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/* Cache sizes */
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@ -1056,6 +1065,20 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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#ifdef CONFIG_NUMA
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#ifdef CONFIG_NUMA
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numa_add_cpu(smp_processor_id());
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numa_add_cpu(smp_processor_id());
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#endif
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#endif
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c->extended_cpuid_level = cpuid_eax(0x80000000);
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if (c->extended_cpuid_level >= 0x80000007)
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c->x86_power = cpuid_edx(0x80000007);
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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early_init_amd(c);
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break;
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case X86_VENDOR_INTEL:
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early_init_intel(c);
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break;
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}
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}
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}
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void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
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void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
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