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drm/amdgpu: add optional dependencies to the CS IOCTL v2
v2: remove unrelated whitespace change, fix C comment Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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03507c4f2f
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2b48d323b2
2 changed files with 67 additions and 1 deletions
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@ -226,6 +226,9 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
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}
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}
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break;
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break;
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case AMDGPU_CHUNK_ID_DEPENDENCIES:
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break;
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default:
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default:
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r = -EINVAL;
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r = -EINVAL;
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goto out;
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goto out;
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@ -663,6 +666,55 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
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return 0;
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return 0;
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}
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}
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static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
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struct amdgpu_cs_parser *p)
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{
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struct amdgpu_ib *ib;
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int i, j, r;
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if (!p->num_ibs)
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return 0;
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/* Add dependencies to first IB */
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ib = &p->ibs[0];
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for (i = 0; i < p->nchunks; ++i) {
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struct drm_amdgpu_cs_chunk_dep *deps;
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struct amdgpu_cs_chunk *chunk;
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unsigned num_deps;
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chunk = &p->chunks[i];
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if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
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continue;
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deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
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num_deps = chunk->length_dw * 4 /
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sizeof(struct drm_amdgpu_cs_chunk_dep);
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for (j = 0; j < num_deps; ++j) {
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struct amdgpu_fence *fence;
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struct amdgpu_ring *ring;
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r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
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deps[j].ip_instance,
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deps[j].ring, &ring);
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if (r)
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return r;
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r = amdgpu_fence_recreate(ring, p->filp,
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deps[j].handle,
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&fence);
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if (r)
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return r;
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amdgpu_sync_fence(&ib->sync, fence);
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amdgpu_fence_unref(&fence);
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}
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}
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return 0;
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}
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int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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{
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{
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_device *adev = dev->dev_private;
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@ -697,11 +749,16 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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else
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else
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DRM_ERROR("Failed to process the buffer list %d!\n", r);
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DRM_ERROR("Failed to process the buffer list %d!\n", r);
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}
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}
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} else {
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}
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if (!r) {
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reserved_buffers = true;
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reserved_buffers = true;
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r = amdgpu_cs_ib_fill(adev, &parser);
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r = amdgpu_cs_ib_fill(adev, &parser);
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}
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}
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if (!r)
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r = amdgpu_cs_dependencies(adev, &parser);
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if (r) {
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if (r) {
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amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
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amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
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up_read(&adev->exclusive_lock);
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up_read(&adev->exclusive_lock);
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@ -348,6 +348,7 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_IB 0x01
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#define AMDGPU_CHUNK_ID_IB 0x01
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#define AMDGPU_CHUNK_ID_FENCE 0x02
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#define AMDGPU_CHUNK_ID_FENCE 0x02
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#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
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struct drm_amdgpu_cs_chunk {
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struct drm_amdgpu_cs_chunk {
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uint32_t chunk_id;
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uint32_t chunk_id;
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@ -399,6 +400,14 @@ struct drm_amdgpu_cs_chunk_ib {
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uint32_t ring;
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uint32_t ring;
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};
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};
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struct drm_amdgpu_cs_chunk_dep {
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uint32_t ip_type;
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uint32_t ip_instance;
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uint32_t ring;
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uint32_t ctx_id;
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uint64_t handle;
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};
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struct drm_amdgpu_cs_chunk_fence {
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struct drm_amdgpu_cs_chunk_fence {
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uint32_t handle;
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uint32_t handle;
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uint32_t offset;
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uint32_t offset;
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