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i.MX drivers update for 5.19:

Browse source 
- A series from Lucas and Paul to update GPCv2 driver for i.MX8MP power
   domains, and add HSIO and HDMI block control support.
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Merge tag 'imx-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers

i.MX drivers update for 5.19:

- A series from Lucas and Paul to update GPCv2 driver for i.MX8MP power
  domains, and add HSIO and HDMI block control support.

* tag 'imx-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx: fix semicolon.cocci warnings
  soc: imx: add i.MX8MP HDMI blk-ctrl
  soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
  soc: imx: add i.MX8MP HSIO blk-ctrl
  dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
  dt-bindings: soc: Add i.MX8MP media block control DT bindings
  soc: imx: imx8m-blk-ctrl: set power device name
  soc: imx: gpcv2: add support for i.MX8MP power domains
  soc: imx: gpcv2: add PGC control register indirection

Link: https://lore.kernel.org/r/20220508033843.2773685-2-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-09 23:10:47 +02:00
commit 2b6866d70d
6 changed files with 1359 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

104
Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml Normal file
View file

@ -0,0 +1,104 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MP Media Block Control
maintainers:
- Paul Elder <paul.elder@ideasonboard.com>
description:
The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
providing access to the NoC and ensuring proper power sequencing of the
peripherals within the MEDIAMIX domain.
properties:
compatible:
items:
- const: fsl,imx8mp-media-blk-ctrl
- const: syscon
reg:
maxItems: 1
'#power-domain-cells':
const: 1
power-domains:
maxItems: 10
power-domain-names:
items:
- const: bus
- const: mipi-dsi1
- const: mipi-csi1
- const: lcdif1
- const: isi
- const: mipi-csi2
- const: lcdif2
- const: isp
- const: dwe
- const: mipi-dsi2
clocks:
items:
- description: The APB clock
- description: The AXI clock
- description: The pixel clock for the first CSI2 receiver (aclk)
- description: The pixel clock for the second CSI2 receiver (aclk)
- description: The pixel clock for the first LCDIF (pix_clk)
- description: The pixel clock for the second LCDIF (pix_clk)
- description: The core clock for the ISP (clk)
- description: The MIPI-PHY reference clock used by DSI
clock-names:
items:
- const: apb
- const: axi
- const: cam1
- const: cam2
- const: disp1
- const: disp2
- const: isp
- const: phy
required:
- compatible
- reg
- '#power-domain-cells'
- power-domains
- power-domain-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
media_blk_ctl: blk-ctl@32ec0000 {
compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
reg = <0x32ec0000 0x138>;
power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
<&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
<&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
<&mipi_phy2_pd>;
power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
"mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
"isp", "phy";
#power-domain-cells = <1>;
};
...

1
drivers/soc/imx/Makefile
View file

@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o

430
drivers/soc/imx/gpcv2.c
View file

@ -21,10 +21,12 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/power/imx8mn-power.h>
#include <dt-bindings/power/imx8mp-power.h>
#define GPC_LPCR_A_CORE_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
@ -65,6 +67,29 @@
#define IMX8MN_OTG1_A53_DOMAIN BIT(4)
#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
#define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
#define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
#define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@ -107,8 +132,30 @@
#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
#define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
#define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
#define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
#define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
#define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
#define IMX8MP_MLMIX_Pxx_REQ BIT(4)
#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
#define GPC_M4_PU_PDN_FLG 0x1bc
#define IMX8MP_GPC_PU_PWRHSK 0x190
#define GPC_PU_PWRHSK 0x1fc
#define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
@ -118,7 +165,6 @@
#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
#define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
#define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
#define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
@ -137,6 +183,21 @@
#define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
#define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
#define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
#define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
#define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@ -179,14 +240,44 @@
#define IMX8MN_PGC_GPUMIX 23
#define IMX8MN_PGC_DISPMIX 26
#define IMX8MP_PGC_NOC 9
#define IMX8MP_PGC_MIPI1 12
#define IMX8MP_PGC_PCIE 13
#define IMX8MP_PGC_USB1 14
#define IMX8MP_PGC_USB2 15
#define IMX8MP_PGC_MLMIX 16
#define IMX8MP_PGC_AUDIOMIX 17
#define IMX8MP_PGC_GPU2D 18
#define IMX8MP_PGC_GPUMIX 19
#define IMX8MP_PGC_VPUMIX 20
#define IMX8MP_PGC_GPU3D 21
#define IMX8MP_PGC_MEDIAMIX 22
#define IMX8MP_PGC_VPU_G1 23
#define IMX8MP_PGC_VPU_G2 24
#define IMX8MP_PGC_VPU_VC8000E 25
#define IMX8MP_PGC_HDMIMIX 26
#define IMX8MP_PGC_HDMI 27
#define IMX8MP_PGC_MIPI2 28
#define IMX8MP_PGC_HSIOMIX 29
#define IMX8MP_PGC_MEDIA_ISP_DWP 30
#define IMX8MP_PGC_DDRMIX 31
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
#define GPC_PGC_CTRL_PCR BIT(0)
struct imx_pgc_regs {
u16 map;
u16 pup;
u16 pdn;
u16 hsk;
};
struct imx_pgc_domain {
struct generic_pm_domain genpd;
struct regmap *regmap;
const struct imx_pgc_regs *regs;
struct regulator *regulator;
struct reset_control *reset;
struct clk_bulk_data *clks;
@ -204,12 +295,16 @@ struct imx_pgc_domain {
const int voltage;
const bool keep_clocks;
struct device *dev;
unsigned int pgc_sw_pup_reg;
unsigned int pgc_sw_pdn_reg;
};
struct imx_pgc_domain_data {
const struct imx_pgc_domain *domains;
size_t domains_num;
const struct regmap_access_table *reg_access_table;
const struct imx_pgc_regs *pgc_regs;
};
static inline struct imx_pgc_domain *
@ -249,14 +344,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
if (domain->bits.pxx) {
/* request the domain to power up */
regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
regmap_update_bits(domain->regmap, domain->regs->pup,
domain->bits.pxx, domain->bits.pxx);
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
ret = regmap_read_poll_timeout(domain->regmap,
GPC_PU_PGC_SW_PUP_REQ, reg_val,
domain->regs->pup, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret) {
@ -278,11 +373,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
/* request the ADB400 to power up */
if (domain->bits.hskreq) {
regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
regmap_update_bits(domain->regmap, domain->regs->hsk,
domain->bits.hskreq, domain->bits.hskreq);
/*
* ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
* ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
* (reg_val & domain->bits.hskack), 0,
* USEC_PER_MSEC);
* Technically we need the commented code to wait handshake. But that needs
@ -329,10 +424,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
/* request the ADB400 to power down */
if (domain->bits.hskreq) {
regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
regmap_clear_bits(domain->regmap, domain->regs->hsk,
domain->bits.hskreq);
ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
reg_val,
!(reg_val & domain->bits.hskack),
0, USEC_PER_MSEC);
@ -350,14 +445,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
}
/* request the domain to power down */
regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
regmap_update_bits(domain->regmap, domain->regs->pdn,
domain->bits.pxx, domain->bits.pxx);
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
ret = regmap_read_poll_timeout(domain->regmap,
GPC_PU_PGC_SW_PDN_REQ, reg_val,
domain->regs->pdn, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret) {
@ -442,10 +537,18 @@ static const struct regmap_access_table imx7_access_table = {
.n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
};
static const struct imx_pgc_regs imx7_pgc_regs = {
.map = GPC_PGC_CPU_MAPPING,
.pup = GPC_PU_PGC_SW_PUP_REQ,
.pdn = GPC_PU_PGC_SW_PDN_REQ,
.hsk = GPC_PU_PWRHSK,
};
static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
.domains = imx7_pgc_domains,
.domains_num = ARRAY_SIZE(imx7_pgc_domains),
.reg_access_table = &imx7_access_table,
.pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8m_pgc_domains[] = {
@ -614,6 +717,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
.domains = imx8m_pgc_domains,
.domains_num = ARRAY_SIZE(imx8m_pgc_domains),
.reg_access_table = &imx8m_access_table,
.pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
@ -804,6 +908,304 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
.domains = imx8mm_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
.reg_access_table = &imx8mm_access_table,
.pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
[IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
.genpd = {
.name = "mipi-phy1",
},
.bits = {
.pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
.map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_MIPI1),
},
[IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
.genpd = {
.name = "pcie-phy1",
},
.bits = {
.pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
.map = IMX8MP_PCIE_PHY_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_PCIE),
},
[IMX8MP_POWER_DOMAIN_USB1_PHY] = {
.genpd = {
.name = "usb-otg1",
},
.bits = {
.pxx = IMX8MP_USB1_PHY_Pxx_REQ,
.map = IMX8MP_USB1_PHY_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_USB1),
},
[IMX8MP_POWER_DOMAIN_USB2_PHY] = {
.genpd = {
.name = "usb-otg2",
},
.bits = {
.pxx = IMX8MP_USB2_PHY_Pxx_REQ,
.map = IMX8MP_USB2_PHY_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_USB2),
},
[IMX8MP_POWER_DOMAIN_MLMIX] = {
.genpd = {
.name = "mlmix",
},
.bits = {
.pxx = IMX8MP_MLMIX_Pxx_REQ,
.map = IMX8MP_MLMIX_A53_DOMAIN,
.hskreq = IMX8MP_MLMIX_PWRDNREQN,
.hskack = IMX8MP_MLMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_MLMIX),
.keep_clocks = true,
},
[IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
.genpd = {
.name = "audiomix",
},
.bits = {
.pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
.map = IMX8MP_AUDIOMIX_A53_DOMAIN,
.hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
.hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_AUDIOMIX),
.keep_clocks = true,
},
[IMX8MP_POWER_DOMAIN_GPU2D] = {
.genpd = {
.name = "gpu2d",
},
.bits = {
.pxx = IMX8MP_GPU_2D_Pxx_REQ,
.map = IMX8MP_GPU2D_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_GPU2D),
},
[IMX8MP_POWER_DOMAIN_GPUMIX] = {
.genpd = {
.name = "gpumix",
},
.bits = {
.pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
.map = IMX8MP_GPUMIX_A53_DOMAIN,
.hskreq = IMX8MP_GPUMIX_PWRDNREQN,
.hskack = IMX8MP_GPUMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_GPUMIX),
.keep_clocks = true,
},
[IMX8MP_POWER_DOMAIN_VPUMIX] = {
.genpd = {
.name = "vpumix",
},
.bits = {
.pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
.map = IMX8MP_VPUMIX_A53_DOMAIN,
.hskreq = IMX8MP_VPUMIX_PWRDNREQN,
.hskack = IMX8MP_VPUMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_VPUMIX),
.keep_clocks = true,
},
[IMX8MP_POWER_DOMAIN_GPU3D] = {
.genpd = {
.name = "gpu3d",
},
.bits = {
.pxx = IMX8MP_GPU_3D_Pxx_REQ,
.map = IMX8MP_GPU3D_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_GPU3D),
},
[IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
.genpd = {
.name = "mediamix",
},
.bits = {
.pxx = IMX8MP_MEDIMIX_Pxx_REQ,
.map = IMX8MP_MEDIAMIX_A53_DOMAIN,
.hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
.hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_MEDIAMIX),
.keep_clocks = true,
},
[IMX8MP_POWER_DOMAIN_VPU_G1] = {
.genpd = {
.name = "vpu-g1",
},
.bits = {
.pxx = IMX8MP_VPU_G1_Pxx_REQ,
.map = IMX8MP_VPU_G1_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_VPU_G1),
},
[IMX8MP_POWER_DOMAIN_VPU_G2] = {
.genpd = {
.name = "vpu-g2",
},
.bits = {
.pxx = IMX8MP_VPU_G2_Pxx_REQ,
.map = IMX8MP_VPU_G2_A53_DOMAIN
},
.pgc = BIT(IMX8MP_PGC_VPU_G2),
},
[IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
.genpd = {
.name = "vpu-h1",
},
.bits = {
.pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
.map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
},
[IMX8MP_POWER_DOMAIN_HDMIMIX] = {
.genpd = {
.name = "hdmimix",
},
.bits = {
.pxx = IMX8MP_HDMIMIX_Pxx_REQ,
.map = IMX8MP_HDMIMIX_A53_DOMAIN,
.hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
.hskack = IMX8MP_HDMIMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_HDMIMIX),
.keep_clocks = true,
},
[IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
.genpd = {
.name = "hdmi-phy",
},
.bits = {
.pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
.map = IMX8MP_HDMI_PHY_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_HDMI),
},
[IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
.genpd = {
.name = "mipi-phy2",
},
.bits = {
.pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
.map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_MIPI2),
},
[IMX8MP_POWER_DOMAIN_HSIOMIX] = {
.genpd = {
.name = "hsiomix",
},
.bits = {
.pxx = IMX8MP_HSIOMIX_Pxx_REQ,
.map = IMX8MP_HSIOMIX_A53_DOMAIN,
.hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
.hskack = IMX8MP_HSIOMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_HSIOMIX),
.keep_clocks = true,
},
[IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
.genpd = {
.name = "mediamix-isp-dwp",
},
.bits = {
.pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
.map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
},
};
static const struct regmap_range imx8mp_yes_ranges[] = {
regmap_reg_range(GPC_LPCR_A_CORE_BSC,
IMX8MP_GPC_PGC_CPU_MAPPING),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
GPC_PGC_SR(IMX8MP_PGC_NOC)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
GPC_PGC_SR(IMX8MP_PGC_PCIE)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
GPC_PGC_SR(IMX8MP_PGC_USB1)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
GPC_PGC_SR(IMX8MP_PGC_USB2)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
GPC_PGC_SR(IMX8MP_PGC_HDMI)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
};
static const struct regmap_access_table imx8mp_access_table = {
.yes_ranges = imx8mp_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
};
static const struct imx_pgc_regs imx8mp_pgc_regs = {
.map = IMX8MP_GPC_PGC_CPU_MAPPING,
.pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
.pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
.hsk = IMX8MP_GPC_PU_PWRHSK,
};
static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
.domains = imx8mp_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
.reg_access_table = &imx8mp_access_table,
.pgc_regs = &imx8mp_pgc_regs,
};
static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
@ -895,6 +1297,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
.domains = imx8mn_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
.reg_access_table = &imx8mn_access_table,
.pgc_regs = &imx7_pgc_regs,
};
static int imx_pgc_domain_probe(struct platform_device *pdev)
@ -927,7 +1330,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
pm_runtime_enable(domain->dev);
if (domain->bits.map)
regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, domain->bits.map);
ret = pm_genpd_init(&domain->genpd, NULL, true);
@ -953,7 +1356,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
pm_genpd_remove(&domain->genpd);
out_domain_unmap:
if (domain->bits.map)
regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, 0);
pm_runtime_disable(domain->dev);
@ -968,7 +1371,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
pm_genpd_remove(&domain->genpd);
if (domain->bits.map)
regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, 0);
pm_runtime_disable(domain->dev);
@ -1099,6 +1502,8 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
domain = pd_pdev->dev.platform_data;
domain->regmap = regmap;
domain->regs = domain_data->pgc_regs;
domain->genpd.power_on = imx_pgc_power_up;
domain->genpd.power_off = imx_pgc_power_down;
@ -1120,6 +1525,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
{ .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
{ }
};

124
drivers/soc/imx/imx8m-blk-ctrl.c
View file

@ -15,11 +15,12 @@
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/power/imx8mn-power.h>
#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/power/imx8mq-power.h>
#define BLK_SFT_RSTN 0x0
#define BLK_CLK_EN 0x4
#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */
#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
struct imx8m_blk_ctrl_domain;
@ -41,7 +42,7 @@ struct imx8m_blk_ctrl_domain_data {
u32 clk_mask;
/*
* i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register
* i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
* which is used to control the reset for the MIPI Phy.
* Since it's only present in certain circumstances,
* an if-statement should be used before setting and clearing this
@ -241,6 +242,7 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
ret = PTR_ERR(domain->power_dev);
goto cleanup_pds;
}
dev_set_name(domain->power_dev, "%s", data->name);
domain->genpd.name = data->name;
domain->genpd.power_on = imx8m_blk_ctrl_power_on;
@ -590,6 +592,121 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
};
static int imx8mp_media_power_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
power_nb);
if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
return NOTIFY_OK;
/* Enable bus clock and deassert bus reset */
regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
/*
* On power up we have no software backchannel to the GPC to
* wait for the ADB handshake to happen, so we just delay for a
* bit. On power down the GPC driver waits for the handshake.
*/
if (action == GENPD_NOTIFY_ON)
udelay(5);
return NOTIFY_OK;
}
/*
* From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
* section 13.2.2, 13.2.3
* isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
*/
static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
[IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
.name = "mediablk-mipi-dsi-1",
.clk_names = (const char *[]){ "apb", "phy", },
.num_clks = 2,
.gpc_name = "mipi-dsi1",
.rst_mask = BIT(0) | BIT(1),
.clk_mask = BIT(0) | BIT(1),
.mipi_phy_rst_mask = BIT(17),
},
[IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
.name = "mediablk-mipi-csi2-1",
.clk_names = (const char *[]){ "apb", "cam1" },
.num_clks = 2,
.gpc_name = "mipi-csi1",
.rst_mask = BIT(2) | BIT(3),
.clk_mask = BIT(2) | BIT(3),
.mipi_phy_rst_mask = BIT(16),
},
[IMX8MP_MEDIABLK_PD_LCDIF_1] = {
.name = "mediablk-lcdif-1",
.clk_names = (const char *[]){ "disp1", "apb", "axi", },
.num_clks = 3,
.gpc_name = "lcdif1",
.rst_mask = BIT(4) | BIT(5) | BIT(23),
.clk_mask = BIT(4) | BIT(5) | BIT(23),
},
[IMX8MP_MEDIABLK_PD_ISI] = {
.name = "mediablk-isi",
.clk_names = (const char *[]){ "axi", "apb" },
.num_clks = 2,
.gpc_name = "isi",
.rst_mask = BIT(6) | BIT(7),
.clk_mask = BIT(6) | BIT(7),
},
[IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
.name = "mediablk-mipi-csi2-2",
.clk_names = (const char *[]){ "apb", "cam2" },
.num_clks = 2,
.gpc_name = "mipi-csi2",
.rst_mask = BIT(9) | BIT(10),
.clk_mask = BIT(9) | BIT(10),
.mipi_phy_rst_mask = BIT(30),
},
[IMX8MP_MEDIABLK_PD_LCDIF_2] = {
.name = "mediablk-lcdif-2",
.clk_names = (const char *[]){ "disp1", "apb", "axi", },
.num_clks = 3,
.gpc_name = "lcdif2",
.rst_mask = BIT(11) | BIT(12) | BIT(24),
.clk_mask = BIT(11) | BIT(12) | BIT(24),
},
[IMX8MP_MEDIABLK_PD_ISP] = {
.name = "mediablk-isp",
.clk_names = (const char *[]){ "isp", "axi", "apb" },
.num_clks = 3,
.gpc_name = "isp",
.rst_mask = BIT(16) | BIT(17) | BIT(18),
.clk_mask = BIT(16) | BIT(17) | BIT(18),
},
[IMX8MP_MEDIABLK_PD_DWE] = {
.name = "mediablk-dwe",
.clk_names = (const char *[]){ "axi", "apb" },
.num_clks = 2,
.gpc_name = "dwe",
.rst_mask = BIT(19) | BIT(20) | BIT(21),
.clk_mask = BIT(19) | BIT(20) | BIT(21),
},
[IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
.name = "mediablk-mipi-dsi-2",
.clk_names = (const char *[]){ "phy", },
.num_clks = 1,
.gpc_name = "mipi-dsi2",
.rst_mask = BIT(22),
.clk_mask = BIT(22),
.mipi_phy_rst_mask = BIT(29),
},
};
static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
.max_reg = 0x138,
.power_notifier_fn = imx8mp_media_power_notifier,
.domains = imx8mp_media_blk_ctl_domain_data,
.num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
};
static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
@ -662,6 +779,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
}, {
.compatible = "fsl,imx8mn-disp-blk-ctrl",
.data = &imx8mn_disp_blk_ctl_dev_data
}, {
.compatible = "fsl,imx8mp-media-blk-ctrl",
.data = &imx8mp_media_blk_ctl_dev_data
}, {
.compatible = "fsl,imx8mq-vpu-blk-ctrl",
.data = &imx8mq_vpu_blk_ctl_dev_data

696
drivers/soc/imx/imx8mp-blk-ctrl.c Normal file
View file

@ -0,0 +1,696 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/power/imx8mp-power.h>
#define GPR_REG0 0x0
#define PCIE_CLOCK_MODULE_EN BIT(0)
#define USB_CLOCK_MODULE_EN BIT(1)
struct imx8mp_blk_ctrl_domain;
struct imx8mp_blk_ctrl {
struct device *dev;
struct notifier_block power_nb;
struct device *bus_power_dev;
struct regmap *regmap;
struct imx8mp_blk_ctrl_domain *domains;
struct genpd_onecell_data onecell_data;
void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
};
struct imx8mp_blk_ctrl_domain_data {
const char *name;
const char * const *clk_names;
int num_clks;
const char *gpc_name;
};
#define DOMAIN_MAX_CLKS 2
struct imx8mp_blk_ctrl_domain {
struct generic_pm_domain genpd;
const struct imx8mp_blk_ctrl_domain_data *data;
struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
struct device *power_dev;
struct imx8mp_blk_ctrl *bc;
int id;
};
struct imx8mp_blk_ctrl_data {
int max_reg;
notifier_fn_t power_notifier_fn;
void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
const struct imx8mp_blk_ctrl_domain_data *domains;
int num_domains;
};
static inline struct imx8mp_blk_ctrl_domain *
to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd)
{
return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd);
}
static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
struct imx8mp_blk_ctrl_domain *domain)
{
switch (domain->id) {
case IMX8MP_HSIOBLK_PD_USB:
regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
break;
case IMX8MP_HSIOBLK_PD_PCIE:
regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
break;
default:
break;
}
}
static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
struct imx8mp_blk_ctrl_domain *domain)
{
switch (domain->id) {
case IMX8MP_HSIOBLK_PD_USB:
regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
break;
case IMX8MP_HSIOBLK_PD_PCIE:
regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
break;
default:
break;
}
}
static int imx8mp_hsio_power_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
power_nb);
struct clk_bulk_data *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clks;
int num_clks = bc->domains[IMX8MP_HSIOBLK_PD_USB].data->num_clks;
int ret;
switch (action) {
case GENPD_NOTIFY_ON:
/*
* enable USB clock for a moment for the power-on ADB handshake
* to proceed
*/
ret = clk_bulk_prepare_enable(num_clks, usb_clk);
if (ret)
return NOTIFY_BAD;
regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
udelay(5);
regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
clk_bulk_disable_unprepare(num_clks, usb_clk);
break;
case GENPD_NOTIFY_PRE_OFF:
/* enable USB clock for the power-down ADB handshake to work */
ret = clk_bulk_prepare_enable(num_clks, usb_clk);
if (ret)
return NOTIFY_BAD;
regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
break;
case GENPD_NOTIFY_OFF:
clk_bulk_disable_unprepare(num_clks, usb_clk);
break;
default:
break;
}
return NOTIFY_OK;
}
static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
[IMX8MP_HSIOBLK_PD_USB] = {
.name = "hsioblk-usb",
.clk_names = (const char *[]){ "usb" },
.num_clks = 1,
.gpc_name = "usb",
},
[IMX8MP_HSIOBLK_PD_USB_PHY1] = {
.name = "hsioblk-usb-phy1",
.gpc_name = "usb-phy1",
},
[IMX8MP_HSIOBLK_PD_USB_PHY2] = {
.name = "hsioblk-usb-phy2",
.gpc_name = "usb-phy2",
},
[IMX8MP_HSIOBLK_PD_PCIE] = {
.name = "hsioblk-pcie",
.clk_names = (const char *[]){ "pcie" },
.num_clks = 1,
.gpc_name = "pcie",
},
[IMX8MP_HSIOBLK_PD_PCIE_PHY] = {
.name = "hsioblk-pcie-phy",
.gpc_name = "pcie-phy",
},
};
static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
.max_reg = 0x24,
.power_on = imx8mp_hsio_blk_ctrl_power_on,
.power_off = imx8mp_hsio_blk_ctrl_power_off,
.power_notifier_fn = imx8mp_hsio_power_notifier,
.domains = imx8mp_hsio_domain_data,
.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
};
#define HDMI_RTX_RESET_CTL0 0x20
#define HDMI_RTX_CLK_CTL0 0x40
#define HDMI_RTX_CLK_CTL1 0x50
#define HDMI_RTX_CLK_CTL2 0x60
#define HDMI_RTX_CLK_CTL3 0x70
#define HDMI_RTX_CLK_CTL4 0x80
#define HDMI_TX_CONTROL0 0x200
static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
struct imx8mp_blk_ctrl_domain *domain)
{
switch (domain->id) {
case IMX8MP_HDMIBLK_PD_IRQSTEER:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
break;
case IMX8MP_HDMIBLK_PD_LCDIF:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
BIT(7) | BIT(16) | BIT(17) | BIT(18) |
BIT(19) | BIT(20));
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
BIT(4) | BIT(5) | BIT(6));
break;
case IMX8MP_HDMIBLK_PD_PAI:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
break;
case IMX8MP_HDMIBLK_PD_PVI:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
break;
case IMX8MP_HDMIBLK_PD_TRNG:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
break;
case IMX8MP_HDMIBLK_PD_HDMI_TX:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
BIT(2) | BIT(4) | BIT(5));
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(18) | BIT(19) | BIT(20) | BIT(21));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
BIT(7) | BIT(10) | BIT(11));
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
break;
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
break;
default:
break;
}
}
static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
struct imx8mp_blk_ctrl_domain *domain)
{
switch (domain->id) {
case IMX8MP_HDMIBLK_PD_IRQSTEER:
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
break;
case IMX8MP_HDMIBLK_PD_LCDIF:
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
BIT(4) | BIT(5) | BIT(6));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
BIT(7) | BIT(16) | BIT(17) | BIT(18) |
BIT(19) | BIT(20));
break;
case IMX8MP_HDMIBLK_PD_PAI:
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
break;
case IMX8MP_HDMIBLK_PD_PVI:
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
break;
case IMX8MP_HDMIBLK_PD_TRNG:
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
break;
case IMX8MP_HDMIBLK_PD_HDMI_TX:
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
BIT(7) | BIT(10) | BIT(11));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(18) | BIT(19) | BIT(20) | BIT(21));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
BIT(2) | BIT(4) | BIT(5));
break;
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
break;
default:
break;
}
}
static int imx8mp_hdmi_power_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
power_nb);
if (action != GENPD_NOTIFY_ON)
return NOTIFY_OK;
/*
* Contrary to other blk-ctrls the reset and clock don't clear when the
* power domain is powered down. To ensure the proper reset pulsing,
* first clear them all to asserted state, then enable the bus clocks
* and then release the ADB reset.
*/
regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
BIT(0) | BIT(1) | BIT(10));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
/*
* On power up we have no software backchannel to the GPC to
* wait for the ADB handshake to happen, so we just delay for a
* bit. On power down the GPC driver waits for the handshake.
*/
udelay(5);
return NOTIFY_OK;
}
static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
[IMX8MP_HDMIBLK_PD_IRQSTEER] = {
.name = "hdmiblk-irqsteer",
.clk_names = (const char *[]){ "apb" },
.num_clks = 1,
.gpc_name = "irqsteer",
},
[IMX8MP_HDMIBLK_PD_LCDIF] = {
.name = "hdmiblk-lcdif",
.clk_names = (const char *[]){ "axi", "apb" },
.num_clks = 2,
.gpc_name = "lcdif",
},
[IMX8MP_HDMIBLK_PD_PAI] = {
.name = "hdmiblk-pai",
.clk_names = (const char *[]){ "apb" },
.num_clks = 1,
.gpc_name = "pai",
},
[IMX8MP_HDMIBLK_PD_PVI] = {
.name = "hdmiblk-pvi",
.clk_names = (const char *[]){ "apb" },
.num_clks = 1,
.gpc_name = "pvi",
},
[IMX8MP_HDMIBLK_PD_TRNG] = {
.name = "hdmiblk-trng",
.clk_names = (const char *[]){ "apb" },
.num_clks = 1,
.gpc_name = "trng",
},
[IMX8MP_HDMIBLK_PD_HDMI_TX] = {
.name = "hdmiblk-hdmi-tx",
.clk_names = (const char *[]){ "apb", "ref_266m" },
.num_clks = 2,
.gpc_name = "hdmi-tx",
},
[IMX8MP_HDMIBLK_PD_HDMI_TX_PHY] = {
.name = "hdmiblk-hdmi-tx-phy",
.clk_names = (const char *[]){ "apb", "ref_24m" },
.num_clks = 2,
.gpc_name = "hdmi-tx-phy",
},
};
static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {
.max_reg = 0x23c,
.power_on = imx8mp_hdmi_blk_ctrl_power_on,
.power_off = imx8mp_hdmi_blk_ctrl_power_off,
.power_notifier_fn = imx8mp_hdmi_power_notifier,
.domains = imx8mp_hdmi_domain_data,
.num_domains = ARRAY_SIZE(imx8mp_hdmi_domain_data),
};
static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
{
struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
struct imx8mp_blk_ctrl *bc = domain->bc;
int ret;
/* make sure bus domain is awake */
ret = pm_runtime_resume_and_get(bc->bus_power_dev);
if (ret < 0) {
dev_err(bc->dev, "failed to power up bus domain\n");
return ret;
}
/* enable upstream clocks */
ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
if (ret) {
dev_err(bc->dev, "failed to enable clocks\n");
goto bus_put;
}
/* domain specific blk-ctrl manipulation */
bc->power_on(bc, domain);
/* power up upstream GPC domain */
ret = pm_runtime_resume_and_get(domain->power_dev);
if (ret < 0) {
dev_err(bc->dev, "failed to power up peripheral domain\n");
goto clk_disable;
}
clk_bulk_disable_unprepare(data->num_clks, domain->clks);
return 0;
clk_disable:
clk_bulk_disable_unprepare(data->num_clks, domain->clks);
bus_put:
pm_runtime_put(bc->bus_power_dev);
return ret;
}
static int imx8mp_blk_ctrl_power_off(struct generic_pm_domain *genpd)
{
struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
struct imx8mp_blk_ctrl *bc = domain->bc;
int ret;
ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
if (ret) {
dev_err(bc->dev, "failed to enable clocks\n");
return ret;
}
/* domain specific blk-ctrl manipulation */
bc->power_off(bc, domain);
clk_bulk_disable_unprepare(data->num_clks, domain->clks);
/* power down upstream GPC domain */
pm_runtime_put(domain->power_dev);
/* allow bus domain to suspend */
pm_runtime_put(bc->bus_power_dev);
return 0;
}
static struct generic_pm_domain *
imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
{
struct genpd_onecell_data *onecell_data = data;
unsigned int index = args->args[0];
if (args->args_count != 1 ||
index >= onecell_data->num_domains)
return ERR_PTR(-EINVAL);
return onecell_data->domains[index];
}
static struct lock_class_key blk_ctrl_genpd_lock_class;
static int imx8mp_blk_ctrl_probe(struct platform_device *pdev)
{
const struct imx8mp_blk_ctrl_data *bc_data;
struct device *dev = &pdev->dev;
struct imx8mp_blk_ctrl *bc;
void __iomem *base;
int num_domains, i, ret;
struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
if (!bc)
return -ENOMEM;
bc->dev = dev;
bc_data = of_device_get_match_data(dev);
num_domains = bc_data->num_domains;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap_config.max_register = bc_data->max_reg;
bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
if (IS_ERR(bc->regmap))
return dev_err_probe(dev, PTR_ERR(bc->regmap),
"failed to init regmap\n");
bc->domains = devm_kcalloc(dev, num_domains,
sizeof(struct imx8mp_blk_ctrl_domain),
GFP_KERNEL);
if (!bc->domains)
return -ENOMEM;
bc->onecell_data.num_domains = num_domains;
bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
bc->onecell_data.domains =
devm_kcalloc(dev, num_domains,
sizeof(struct generic_pm_domain *), GFP_KERNEL);
if (!bc->onecell_data.domains)
return -ENOMEM;
bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
if (IS_ERR(bc->bus_power_dev))
return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
"failed to attach bus power domain\n");
bc->power_off = bc_data->power_off;
bc->power_on = bc_data->power_on;
for (i = 0; i < num_domains; i++) {
const struct imx8mp_blk_ctrl_domain_data *data = &bc_data->domains[i];
struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
int j;
domain->data = data;
for (j = 0; j < data->num_clks; j++)
domain->clks[j].id = data->clk_names[j];
ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
if (ret) {
dev_err_probe(dev, ret, "failed to get clock\n");
goto cleanup_pds;
}
domain->power_dev =
dev_pm_domain_attach_by_name(dev, data->gpc_name);
if (IS_ERR(domain->power_dev)) {
dev_err_probe(dev, PTR_ERR(domain->power_dev),
"failed to attach power domain %s\n",
data->gpc_name);
ret = PTR_ERR(domain->power_dev);
goto cleanup_pds;
}
dev_set_name(domain->power_dev, "%s", data->name);
domain->genpd.name = data->name;
domain->genpd.power_on = imx8mp_blk_ctrl_power_on;
domain->genpd.power_off = imx8mp_blk_ctrl_power_off;
domain->bc = bc;
domain->id = i;
ret = pm_genpd_init(&domain->genpd, NULL, true);
if (ret) {
dev_err_probe(dev, ret, "failed to init power domain\n");
dev_pm_domain_detach(domain->power_dev, true);
goto cleanup_pds;
}
/*
* We use runtime PM to trigger power on/off of the upstream GPC
* domain, as a strict hierarchical parent/child power domain
* setup doesn't allow us to meet the sequencing requirements.
* This means we have nested locking of genpd locks, without the
* nesting being visible at the genpd level, so we need a
* separate lock class to make lockdep aware of the fact that
* this are separate domain locks that can be nested without a
* self-deadlock.
*/
lockdep_set_class(&domain->genpd.mlock,
&blk_ctrl_genpd_lock_class);
bc->onecell_data.domains[i] = &domain->genpd;
}
ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
if (ret) {
dev_err_probe(dev, ret, "failed to add power domain provider\n");
goto cleanup_pds;
}
bc->power_nb.notifier_call = bc_data->power_notifier_fn;
ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
if (ret) {
dev_err_probe(dev, ret, "failed to add power notifier\n");
goto cleanup_provider;
}
dev_set_drvdata(dev, bc);
return 0;
cleanup_provider:
of_genpd_del_provider(dev->of_node);
cleanup_pds:
for (i--; i >= 0; i--) {
pm_genpd_remove(&bc->domains[i].genpd);
dev_pm_domain_detach(bc->domains[i].power_dev, true);
}
dev_pm_domain_detach(bc->bus_power_dev, true);
return ret;
}
static int imx8mp_blk_ctrl_remove(struct platform_device *pdev)
{
struct imx8mp_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
int i;
of_genpd_del_provider(pdev->dev.of_node);
for (i = 0; bc->onecell_data.num_domains; i++) {
struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
pm_genpd_remove(&domain->genpd);
dev_pm_domain_detach(domain->power_dev, true);
}
dev_pm_genpd_remove_notifier(bc->bus_power_dev);
dev_pm_domain_detach(bc->bus_power_dev, true);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int imx8mp_blk_ctrl_suspend(struct device *dev)
{
struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
int ret, i;
/*
* This may look strange, but is done so the generic PM_SLEEP code
* can power down our domains and more importantly power them up again
* after resume, without tripping over our usage of runtime PM to
* control the upstream GPC domains. Things happen in the right order
* in the system suspend/resume paths due to the device parent/child
* hierarchy.
*/
ret = pm_runtime_get_sync(bc->bus_power_dev);
if (ret < 0) {
pm_runtime_put_noidle(bc->bus_power_dev);
return ret;
}
for (i = 0; i < bc->onecell_data.num_domains; i++) {
struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
ret = pm_runtime_get_sync(domain->power_dev);
if (ret < 0) {
pm_runtime_put_noidle(domain->power_dev);
goto out_fail;
}
}
return 0;
out_fail:
for (i--; i >= 0; i--)
pm_runtime_put(bc->domains[i].power_dev);
pm_runtime_put(bc->bus_power_dev);
return ret;
}
static int imx8mp_blk_ctrl_resume(struct device *dev)
{
struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
int i;
for (i = 0; i < bc->onecell_data.num_domains; i++)
pm_runtime_put(bc->domains[i].power_dev);
pm_runtime_put(bc->bus_power_dev);
return 0;
}
#endif
static const struct dev_pm_ops imx8mp_blk_ctrl_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(imx8mp_blk_ctrl_suspend,
imx8mp_blk_ctrl_resume)
};
static const struct of_device_id imx8mp_blk_ctrl_of_match[] = {
{
.compatible = "fsl,imx8mp-hsio-blk-ctrl",
.data = &imx8mp_hsio_blk_ctl_dev_data,
}, {
.compatible = "fsl,imx8mp-hdmi-blk-ctrl",
.data = &imx8mp_hdmi_blk_ctl_dev_data,
}, {
/* Sentinel */
}
};
MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
static struct platform_driver imx8mp_blk_ctrl_driver = {
.probe = imx8mp_blk_ctrl_probe,
.remove = imx8mp_blk_ctrl_remove,
.driver = {
.name = "imx8mp-blk-ctrl",
.pm = &imx8mp_blk_ctrl_pm_ops,
.of_match_table = imx8mp_blk_ctrl_of_match,
},
};
module_platform_driver(imx8mp_blk_ctrl_driver);

18
include/dt-bindings/power/imx8mp-power.h
View file

@ -32,4 +32,22 @@
#define IMX8MP_HSIOBLK_PD_PCIE 3
#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
#define IMX8MP_MEDIABLK_PD_ISI 3
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
#define IMX8MP_MEDIABLK_PD_ISP 6
#define IMX8MP_MEDIABLK_PD_DWE 7
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
#define IMX8MP_HDMIBLK_PD_IRQSTEER 0
#define IMX8MP_HDMIBLK_PD_LCDIF 1
#define IMX8MP_HDMIBLK_PD_PAI 2
#define IMX8MP_HDMIBLK_PD_PVI 3
#define IMX8MP_HDMIBLK_PD_TRNG 4
#define IMX8MP_HDMIBLK_PD_HDMI_TX 5
#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
#endif