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sata_mv: implement IRQ coalescing (v2)
Add IRQ coalescing to sata_mv (off by default). This feature can reduce total interrupt overhead for RAID setups in some situations, by deferring the interrupt signal until one or both of: a) a specified io_count (completed SATA commands) is achieved, or b) a specified time interval elapses after an IO completion. For now, module parameters are used to set the irq_coalescing_io_count and irq_coalescing_usecs (timeout) globally. These may eventually be supplemented with sysfs attributes, so that thresholds can be set on-the-fly and on a per-chip (or even per-host_controller) basis. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
parent
40f21b1124
commit
2b748a0a34
1 changed files with 135 additions and 8 deletions
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@ -34,10 +34,7 @@
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*
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* --> Develop a low-power-consumption strategy, and implement it.
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*
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* --> [Experiment, low priority] Investigate interrupt coalescing.
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* Quite often, especially with PCI Message Signalled Interrupts (MSI),
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* the overhead reduced by interrupt mitigation is quite often not
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* worth the latency cost.
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* --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
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*
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* --> [Experiment, Marvell value added] Is it possible to use target
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* mode to cross-connect two Linux boxes with Marvell cards? If so,
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@ -67,7 +64,7 @@
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#include <linux/libata.h>
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#define DRV_NAME "sata_mv"
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#define DRV_VERSION "1.26"
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#define DRV_VERSION "1.27"
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/*
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* module options
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@ -79,6 +76,16 @@ module_param(msi, int, S_IRUGO);
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MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
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#endif
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static int irq_coalescing_io_count;
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module_param(irq_coalescing_io_count, int, S_IRUGO);
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MODULE_PARM_DESC(irq_coalescing_io_count,
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"IRQ coalescing I/O count threshold (0..255)");
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static int irq_coalescing_usecs;
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module_param(irq_coalescing_usecs, int, S_IRUGO);
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MODULE_PARM_DESC(irq_coalescing_usecs,
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"IRQ coalescing time threshold in usecs");
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enum {
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/* BAR's are enumerated in terms of pci_resource_start() terms */
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MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
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@ -88,8 +95,33 @@ enum {
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MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
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MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
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/* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
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COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
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MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
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MAX_COAL_IO_COUNT = 255, /* completed I/O count */
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MV_PCI_REG_BASE = 0,
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/*
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* Per-chip ("all ports") interrupt coalescing feature.
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* This is only for GEN_II / GEN_IIE hardware.
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*
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* Coalescing defers the interrupt until either the IO_THRESHOLD
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* (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
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*/
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MV_COAL_REG_BASE = 0x18000,
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MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08),
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ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
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MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc),
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MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0),
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/*
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* Registers for the (unused here) transaction coalescing feature:
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*/
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MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88),
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MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c),
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MV_SATAHC0_REG_BASE = 0x20000,
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MV_FLASH_CTL_OFS = 0x1046c,
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MV_GPIO_PORT_CTL_OFS = 0x104f0,
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@ -186,6 +218,8 @@ enum {
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DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
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HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
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HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
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DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
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DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
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PCI_ERR = (1 << 18),
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TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
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TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
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@ -207,6 +241,16 @@ enum {
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HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
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DEV_IRQ = (1 << 8), /* shift by port # */
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/*
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* Per-HC (Host-Controller) interrupt coalescing feature.
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* This is present on all chip generations.
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*
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* Coalescing defers the interrupt until either the IO_THRESHOLD
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* (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
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*/
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HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c,
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HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010,
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/* Shadow block registers */
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SHD_BLK_OFS = 0x100,
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SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
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@ -897,6 +941,23 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio,
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port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
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}
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static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
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{
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/*
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* When writing to the main_irq_mask in hardware,
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* we must ensure exclusivity between the interrupt coalescing bits
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* and the corresponding individual port DONE_IRQ bits.
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*
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* Note that this register is really an "IRQ enable" register,
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* not an "IRQ mask" register as Marvell's naming might suggest.
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*/
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if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
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mask &= ~DONE_IRQ_0_3;
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if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
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mask &= ~DONE_IRQ_4_7;
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writelfl(mask, hpriv->main_irq_mask_addr);
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}
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static void mv_set_main_irq_mask(struct ata_host *host,
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u32 disable_bits, u32 enable_bits)
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{
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@ -907,7 +968,7 @@ static void mv_set_main_irq_mask(struct ata_host *host,
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new_mask = (old_mask & ~disable_bits) | enable_bits;
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if (new_mask != old_mask) {
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hpriv->main_irq_mask = new_mask;
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writelfl(new_mask, hpriv->main_irq_mask_addr);
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mv_write_main_irq_mask(new_mask, hpriv);
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}
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}
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@ -948,6 +1009,64 @@ static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
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mv_enable_port_irqs(ap, port_irqs);
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}
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static void mv_set_irq_coalescing(struct ata_host *host,
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unsigned int count, unsigned int usecs)
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{
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struct mv_host_priv *hpriv = host->private_data;
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void __iomem *mmio = hpriv->base, *hc_mmio;
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u32 coal_enable = 0;
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unsigned long flags;
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unsigned int clks;
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const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
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ALL_PORTS_COAL_DONE;
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/* Disable IRQ coalescing if either threshold is zero */
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if (!usecs || !count) {
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clks = count = 0;
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} else {
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/* Respect maximum limits of the hardware */
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clks = usecs * COAL_CLOCKS_PER_USEC;
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if (clks > MAX_COAL_TIME_THRESHOLD)
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clks = MAX_COAL_TIME_THRESHOLD;
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if (count > MAX_COAL_IO_COUNT)
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count = MAX_COAL_IO_COUNT;
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}
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spin_lock_irqsave(&host->lock, flags);
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#if 0 /* disabled pending functional clarification from Marvell */
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if (!IS_GEN_I(hpriv)) {
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/*
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* GEN_II/GEN_IIE: global thresholds for the entire chip.
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*/
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writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD);
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writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD);
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/* clear leftover coal IRQ bit */
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writelfl(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
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clks = count = 0; /* so as to clear the alternate regs below */
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coal_enable = ALL_PORTS_COAL_DONE;
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}
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#endif
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/*
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* All chips: independent thresholds for each HC on the chip.
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*/
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hc_mmio = mv_hc_base_from_port(mmio, 0);
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writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
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writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
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coal_enable |= PORTS_0_3_COAL_DONE;
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if (hpriv->n_ports > 4) {
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hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
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writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
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writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
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coal_enable |= PORTS_4_7_COAL_DONE;
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}
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if (!count)
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coal_enable = 0;
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mv_set_main_irq_mask(host, coal_disable, coal_enable);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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/**
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* mv_start_edma - Enable eDMA engine
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* @base: port base address
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@ -2500,6 +2619,10 @@ static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
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void __iomem *mmio = hpriv->base, *hc_mmio;
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unsigned int handled = 0, port;
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/* If asserted, clear the "all ports" IRQ coalescing bit */
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if (main_irq_cause & ALL_PORTS_COAL_DONE)
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writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
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for (port = 0; port < hpriv->n_ports; port++) {
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struct ata_port *ap = host->ports[port];
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unsigned int p, shift, hardport, port_cause;
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@ -2532,6 +2655,8 @@ static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
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* to ack (only) those ports via hc_irq_cause.
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*/
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ack_irqs = 0;
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if (hc_cause & PORTS_0_3_COAL_DONE)
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ack_irqs = HC_COAL_IRQ;
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for (p = 0; p < MV_PORTS_PER_HC; ++p) {
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if ((port + p) >= hpriv->n_ports)
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break;
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@ -2620,7 +2745,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
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/* for MSI: block new interrupts while in here */
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if (using_msi)
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writel(0, hpriv->main_irq_mask_addr);
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mv_write_main_irq_mask(0, hpriv);
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main_irq_cause = readl(hpriv->main_irq_cause_addr);
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pending_irqs = main_irq_cause & hpriv->main_irq_mask;
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@ -2637,7 +2762,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
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/* for MSI: unmask; interrupt cause bits will retrigger now */
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if (using_msi)
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writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
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mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
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spin_unlock(&host->lock);
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@ -3546,6 +3671,8 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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* The per-port interrupts get done later as ports are set up.
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*/
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mv_set_main_irq_mask(host, 0, PCI_ERR);
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mv_set_irq_coalescing(host, irq_coalescing_io_count,
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irq_coalescing_usecs);
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done:
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return rc;
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}
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