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drm/i915: Reserve ioctl numbers for set/get_caching
I'm planing to merge this next week for 3.7, but I'd like to avoid stupid conflicts with the exsting userspace when merging the new reg_read ioctl (which doesn't have userspace yet, but this caching interface has). Header extracted from Chris Wilson's patch, but fix up the copy&pasted comment in the interface struct. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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1 changed files with 15 additions and 0 deletions
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@ -203,6 +203,8 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_GEM_WAIT 0x2c
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#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
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#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
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#define DRM_I915_GEM_SET_CACHEING 0x2f
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#define DRM_I915_GEM_GET_CACHEING 0x30
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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@ -227,6 +229,8 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
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#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
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#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
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#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing)
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#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing)
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#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
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#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
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#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
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@ -702,6 +706,17 @@ struct drm_i915_gem_busy {
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__u32 busy;
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};
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#define I915_CACHEING_NONE 0
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#define I915_CACHEING_CACHED 1
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struct drm_i915_gem_cacheing {
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/** Handle of the buffer to check for busy */
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__u32 handle;
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/** Cacheing level to apply or return value */
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__u32 cacheing;
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};
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#define I915_TILING_NONE 0
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#define I915_TILING_X 1
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#define I915_TILING_Y 2
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