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clk: renesas: rcar-gen3: Always use readl()/writel()
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of
clk_readl()/clk_writel() and readl()/writel() to access the clock
registers. Settle on the generic readl()/writel().
Cfr. commit 30ad3cf00e
("clk: renesas: rcar-gen3-cpg: Always use
readl()/writel()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
parent
f046d6a6bf
commit
2b935d524d
1 changed files with 7 additions and 7 deletions
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@ -93,7 +93,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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unsigned int mult;
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u32 val;
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val = clk_readl(zclk->reg) & zclk->mask;
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val = readl(zclk->reg) & zclk->mask;
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mult = 32 - (val >> __ffs(zclk->mask));
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/* Factor of 2 is for fixed divider */
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@ -125,20 +125,20 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
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mult = clamp(mult, 1U, 32U);
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if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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val = clk_readl(zclk->reg) & ~zclk->mask;
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val = readl(zclk->reg) & ~zclk->mask;
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val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
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clk_writel(val, zclk->reg);
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writel(val, zclk->reg);
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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kick = clk_readl(zclk->kick_reg);
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kick = readl(zclk->kick_reg);
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kick |= CPG_FRQCRB_KICK;
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clk_writel(kick, zclk->kick_reg);
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writel(kick, zclk->kick_reg);
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/*
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* Note: There is no HW information about the worst case latency.
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@ -150,7 +150,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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* "super" safe value.
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*/
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for (i = 1000; i; i--) {
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if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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return 0;
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cpu_relax();
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