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watchdog: s3c2410: Extract disable and mask code into separate functions
The s3c2410wdt_mask_and_disable_reset() function content is bound to be changed further. Prepare it for upcoming changes by splitting into separate "mask reset" and "disable reset" functions. But keep s3c2410wdt_mask_and_disable_reset() function present as a facade. This commit doesn't bring any functional change to existing devices, but merely provides an infrastructure for upcoming chips support. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20211107202943.8859-7-semen.protsenko@linaro.org Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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parent
8d9fdf60e3
commit
2bd33bb4bc
1 changed files with 38 additions and 22 deletions
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@ -202,37 +202,53 @@ static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
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return container_of(nb, struct s3c2410_wdt, freq_transition);
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return container_of(nb, struct s3c2410_wdt, freq_transition);
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}
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}
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static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
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static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
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{
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{
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const u32 mask_val = BIT(wdt->drv_data->mask_bit);
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const u32 val = mask ? mask_val : 0;
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int ret;
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int ret;
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u32 mask_val = 1 << wdt->drv_data->mask_bit;
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u32 val = 0;
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/* No need to do anything if no PMU CONFIG needed */
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ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,
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if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
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return 0;
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if (mask)
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val = mask_val;
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if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
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ret = regmap_update_bits(wdt->pmureg,
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wdt->drv_data->disable_reg, mask_val,
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val);
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if (ret < 0)
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goto error;
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}
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ret = regmap_update_bits(wdt->pmureg,
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wdt->drv_data->mask_reset_reg,
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mask_val, val);
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mask_val, val);
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error:
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if (ret < 0)
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if (ret < 0)
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dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
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dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
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return ret;
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return ret;
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}
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}
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static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
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{
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const u32 mask_val = BIT(wdt->drv_data->mask_bit);
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const u32 val = mask ? mask_val : 0;
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int ret;
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ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,
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mask_val, val);
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if (ret < 0)
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dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
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return ret;
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}
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static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
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{
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int ret;
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if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
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ret = s3c2410wdt_disable_wdt_reset(wdt, mask);
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if (ret < 0)
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return ret;
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}
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if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG) {
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ret = s3c2410wdt_mask_wdt_reset(wdt, mask);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
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static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
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{
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{
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
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