mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-22 17:01:14 +00:00
Merge commit 'v3.1' into devicetree/next
This commit is contained in:
commit
2bf6f675fa
153 changed files with 955 additions and 603 deletions
|
@ -2706,10 +2706,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
functions are at fixed addresses, they make nice
|
||||
targets for exploits that can control RIP.
|
||||
|
||||
emulate [default] Vsyscalls turn into traps and are
|
||||
emulated reasonably safely.
|
||||
emulate Vsyscalls turn into traps and are emulated
|
||||
reasonably safely.
|
||||
|
||||
native Vsyscalls are native syscall instructions.
|
||||
native [default] Vsyscalls are native syscall
|
||||
instructions.
|
||||
This is a little bit faster than trapping
|
||||
and makes a few dynamic recompilers work
|
||||
better than they would in emulation mode.
|
||||
|
|
|
@ -27,7 +27,7 @@ applying a filter to each packet that assigns it to one of a small number
|
|||
of logical flows. Packets for each flow are steered to a separate receive
|
||||
queue, which in turn can be processed by separate CPUs. This mechanism is
|
||||
generally known as “Receive-side Scaling” (RSS). The goal of RSS and
|
||||
the other scaling techniques to increase performance uniformly.
|
||||
the other scaling techniques is to increase performance uniformly.
|
||||
Multi-queue distribution can also be used for traffic prioritization, but
|
||||
that is not the focus of these techniques.
|
||||
|
||||
|
@ -186,10 +186,10 @@ are steered using plain RPS. Multiple table entries may point to the
|
|||
same CPU. Indeed, with many flows and few CPUs, it is very likely that
|
||||
a single application thread handles flows with many different flow hashes.
|
||||
|
||||
rps_sock_table is a global flow table that contains the *desired* CPU for
|
||||
flows: the CPU that is currently processing the flow in userspace. Each
|
||||
table value is a CPU index that is updated during calls to recvmsg and
|
||||
sendmsg (specifically, inet_recvmsg(), inet_sendmsg(), inet_sendpage()
|
||||
rps_sock_flow_table is a global flow table that contains the *desired* CPU
|
||||
for flows: the CPU that is currently processing the flow in userspace.
|
||||
Each table value is a CPU index that is updated during calls to recvmsg
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||||
and sendmsg (specifically, inet_recvmsg(), inet_sendmsg(), inet_sendpage()
|
||||
and tcp_splice_read()).
|
||||
|
||||
When the scheduler moves a thread to a new CPU while it has outstanding
|
||||
|
|
|
@ -2460,7 +2460,7 @@ S: Supported
|
|||
F: drivers/infiniband/hw/ehca/
|
||||
|
||||
EHEA (IBM pSeries eHEA 10Gb ethernet adapter) DRIVER
|
||||
M: Breno Leitao <leitao@linux.vnet.ibm.com>
|
||||
M: Thadeu Lima de Souza Cascardo <cascardo@linux.vnet.ibm.com>
|
||||
L: netdev@vger.kernel.org
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||||
S: Maintained
|
||||
F: drivers/net/ehea/
|
||||
|
@ -3313,7 +3313,7 @@ M: David Woodhouse <dwmw2@infradead.org>
|
|||
L: iommu@lists.linux-foundation.org
|
||||
T: git git://git.infradead.org/iommu-2.6.git
|
||||
S: Supported
|
||||
F: drivers/pci/intel-iommu.c
|
||||
F: drivers/iommu/intel-iommu.c
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||||
F: include/linux/intel-iommu.h
|
||||
|
||||
INTEL IOP-ADMA DMA DRIVER
|
||||
|
@ -6368,10 +6368,10 @@ F: net/ipv4/tcp_lp.c
|
|||
|
||||
TEGRA SUPPORT
|
||||
M: Colin Cross <ccross@android.com>
|
||||
M: Erik Gilling <konkers@android.com>
|
||||
M: Olof Johansson <olof@lixom.net>
|
||||
M: Stephen Warren <swarren@nvidia.com>
|
||||
L: linux-tegra@vger.kernel.org
|
||||
T: git git://android.git.kernel.org/kernel/tegra.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
|
||||
S: Supported
|
||||
F: arch/arm/mach-tegra
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 1
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc9
|
||||
EXTRAVERSION =
|
||||
NAME = "Divemaster Edition"
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -259,7 +259,6 @@ static void __init vic_disable(void __iomem *base)
|
|||
writel(0, base + VIC_INT_SELECT);
|
||||
writel(0, base + VIC_INT_ENABLE);
|
||||
writel(~0, base + VIC_INT_ENABLE_CLEAR);
|
||||
writel(0, base + VIC_IRQ_STATUS);
|
||||
writel(0, base + VIC_ITCR);
|
||||
writel(~0, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
#ifndef __ASM_ARM_LOCALTIMER_H
|
||||
#define __ASM_ARM_LOCALTIMER_H
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
struct clock_event_device;
|
||||
|
||||
/*
|
||||
|
|
|
@ -321,8 +321,8 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
|
|||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] =
|
||||
ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
|
||||
|
|
|
@ -193,7 +193,8 @@ static int __init omap2430_i2c_init(void)
|
|||
{
|
||||
omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
|
||||
ARRAY_SIZE(sdp2430_i2c1_boardinfo));
|
||||
omap2_pmic_init("twl4030", &sdp2430_twldata);
|
||||
omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
|
||||
&sdp2430_twldata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -137,8 +137,7 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
|
|||
*/
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
|
||||
|
@ -156,8 +155,7 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
|||
else
|
||||
reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(5);
|
||||
|
@ -171,16 +169,14 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
|||
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
|
||||
pr_err("Pbias Voltage is not same as LDO\n");
|
||||
/* Caution : On VMODE_ERROR Power Down MMC IO */
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
} else {
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -137,9 +137,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
|
|||
musb_plat.mode = board_data->mode;
|
||||
musb_plat.extvbus = board_data->extvbus;
|
||||
|
||||
if (cpu_is_omap44xx())
|
||||
omap4430_phy_init(dev);
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505()) {
|
||||
oh_name = "am35x_otg_hs";
|
||||
name = "musb-am35x";
|
||||
|
|
|
@ -170,7 +170,9 @@ int __init s3c2410_init(void)
|
|||
{
|
||||
printk("S3C2410: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2410_sysdev);
|
||||
|
|
|
@ -245,7 +245,9 @@ int __init s3c2412_init(void)
|
|||
{
|
||||
printk("S3C2412: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2412_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2412_sysdev);
|
||||
|
|
|
@ -97,7 +97,9 @@ int __init s3c2416_init(void)
|
|||
|
||||
s3c_fb_setname("s3c2443-fb");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2416_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2416_sysdev);
|
||||
|
|
|
@ -55,7 +55,9 @@ int __init s3c2440_init(void)
|
|||
|
||||
/* register suspend/resume handlers */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
|
|
|
@ -169,7 +169,9 @@ int __init s3c2442_init(void)
|
|||
{
|
||||
printk("S3C2442: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
|
|
|
@ -32,7 +32,6 @@
|
|||
|
||||
#include <asm/system.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/clk.h>
|
||||
|
||||
/* Frequency table index must be sequential starting at 0 */
|
||||
|
|
|
@ -6,6 +6,7 @@ config UX500_SOC_COMMON
|
|||
select ARM_GIC
|
||||
select HAS_MTU
|
||||
select ARM_ERRATA_753970
|
||||
select ARM_ERRATA_754322
|
||||
|
||||
menu "Ux500 SoC"
|
||||
|
||||
|
|
|
@ -496,6 +496,13 @@ static void __init free_unused_memmap(struct meminfo *mi)
|
|||
*/
|
||||
bank_start = min(bank_start,
|
||||
ALIGN(prev_bank_end, PAGES_PER_SECTION));
|
||||
#else
|
||||
/*
|
||||
* Align down here since the VM subsystem insists that the
|
||||
* memmap entries are valid from the bank start aligned to
|
||||
* MAX_ORDER_NR_PAGES.
|
||||
*/
|
||||
bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
|
||||
#endif
|
||||
/*
|
||||
* If we had a previous bank, and there is a space
|
||||
|
|
|
@ -163,9 +163,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
|
|||
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_set_type = s5p_gpioint_set_type,
|
||||
ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
|
||||
irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
|
||||
IRQ_GC_INIT_MASK_CACHE,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
||||
|
|
|
@ -24,6 +24,7 @@ config MIPS
|
|||
select GENERIC_IRQ_PROBE
|
||||
select GENERIC_IRQ_SHOW
|
||||
select HAVE_ARCH_JUMP_LABEL
|
||||
select IRQ_FORCED_THREADING
|
||||
|
||||
menu "Machine selection"
|
||||
|
||||
|
@ -722,6 +723,7 @@ config CAVIUM_OCTEON_SIMULATOR
|
|||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_SUPPORTS_HOTPLUG_CPU
|
||||
select SYS_HAS_CPU_CAVIUM_OCTEON
|
||||
select HOLES_IN_ZONE
|
||||
help
|
||||
The Octeon simulator is software performance model of the Cavium
|
||||
Octeon Processor. It supports simulating Octeon processors on x86
|
||||
|
@ -744,6 +746,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
|
|||
select ZONE_DMA32
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
select HOLES_IN_ZONE
|
||||
help
|
||||
This option supports all of the Octeon reference boards from Cavium
|
||||
Networks. It builds a kernel that dynamically determines the Octeon
|
||||
|
@ -973,6 +976,9 @@ config ISA_DMA_API
|
|||
config GENERIC_GPIO
|
||||
bool
|
||||
|
||||
config HOLES_IN_ZONE
|
||||
bool
|
||||
|
||||
#
|
||||
# Endianess selection. Sufficiently obscure so many users don't know what to
|
||||
# answer,so we try hard to limit the available choices. Also the use of a
|
||||
|
|
|
@ -492,7 +492,7 @@ static void __init alchemy_setup_macs(int ctype)
|
|||
memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
|
||||
|
||||
ret = platform_device_register(&au1xxx_eth0_device);
|
||||
if (!ret)
|
||||
if (ret)
|
||||
printk(KERN_INFO "Alchemy: failed to register MAC0\n");
|
||||
|
||||
|
||||
|
|
|
@ -158,15 +158,21 @@ static void restore_core_regs(void)
|
|||
|
||||
void au_sleep(void)
|
||||
{
|
||||
int cpuid = alchemy_get_cputype();
|
||||
if (cpuid != ALCHEMY_CPU_UNKNOWN) {
|
||||
save_core_regs();
|
||||
if (cpuid <= ALCHEMY_CPU_AU1500)
|
||||
alchemy_sleep_au1000();
|
||||
else if (cpuid <= ALCHEMY_CPU_AU1200)
|
||||
alchemy_sleep_au1550();
|
||||
restore_core_regs();
|
||||
save_core_regs();
|
||||
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000:
|
||||
case ALCHEMY_CPU_AU1500:
|
||||
case ALCHEMY_CPU_AU1100:
|
||||
alchemy_sleep_au1000();
|
||||
break;
|
||||
case ALCHEMY_CPU_AU1550:
|
||||
case ALCHEMY_CPU_AU1200:
|
||||
alchemy_sleep_au1550();
|
||||
break;
|
||||
}
|
||||
|
||||
restore_core_regs();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
|
|
@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
|
|||
{
|
||||
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
for ( ; bisr; bisr &= bisr - 1)
|
||||
generic_handle_irq(bcsr_csc_base + __ffs(bisr));
|
||||
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
/* NOTE: both the enable and mask bits must be cleared, otherwise the
|
||||
|
|
|
@ -23,13 +23,6 @@ void __init board_setup(void)
|
|||
unsigned long freq0, clksrc, div, pfc;
|
||||
unsigned short whoami;
|
||||
|
||||
/* Set Config[OD] (disable overlapping bus transaction):
|
||||
* This gets rid of a _lot_ of spurious interrupts (especially
|
||||
* wrt. IDE); but incurs ~10% performance hit in some
|
||||
* cpu-bound applications.
|
||||
*/
|
||||
set_c0_config(1 << 19);
|
||||
|
||||
bcsr_init(DB1200_BCSR_PHYS_ADDR,
|
||||
DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
|
||||
|
||||
|
|
|
@ -98,7 +98,8 @@ static struct irq_chip ar7_sec_irq_type = {
|
|||
|
||||
static struct irqaction ar7_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "AR7 cascade interrupt"
|
||||
.name = "AR7 cascade interrupt",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static void __init ar7_irq_init(int base)
|
||||
|
|
|
@ -222,6 +222,7 @@ static struct irq_chip bcm63xx_external_irq_chip = {
|
|||
static struct irqaction cpu_ip2_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "cascade_ip2",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -48,6 +48,7 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
static struct irqaction cascade = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -101,20 +101,24 @@ int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
|
|||
static struct irqaction ioirq = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
static struct irqaction fpuirq = {
|
||||
.handler = no_action,
|
||||
.name = "fpu",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction busirq = {
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "bus error",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction haltirq = {
|
||||
.handler = dec_intr_halt,
|
||||
.name = "halt",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -169,7 +169,7 @@ void emma2rh_gpio_irq_init(void)
|
|||
|
||||
static struct irqaction irq_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = 0,
|
||||
.flags = IRQF_NO_THREAD,
|
||||
.name = "cascade",
|
||||
.dev_id = NULL,
|
||||
.next = NULL,
|
||||
|
|
|
@ -54,7 +54,6 @@
|
|||
#define cpu_has_mips_r2_exec_hazard 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_userlocal 0
|
||||
#define cpu_has_vint 0
|
||||
#define cpu_has_veic 0
|
||||
#define cpu_hwrena_impl_bits 0xc0000000
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/device.h>
|
||||
#include <asm/mach-powertv/asic.h>
|
||||
|
||||
|
|
|
@ -195,9 +195,9 @@
|
|||
* to cover the pipeline delay.
|
||||
*/
|
||||
.set mips32
|
||||
mfc0 v1, CP0_TCSTATUS
|
||||
mfc0 k0, CP0_TCSTATUS
|
||||
.set mips0
|
||||
LONG_S v1, PT_TCSTATUS(sp)
|
||||
LONG_S k0, PT_TCSTATUS(sp)
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
LONG_S $4, PT_R4(sp)
|
||||
LONG_S $5, PT_R5(sp)
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
#include <linux/init.h>
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
|
@ -86,7 +86,6 @@ struct jz_gpio_chip {
|
|||
spinlock_t lock;
|
||||
|
||||
struct gpio_chip gpio_chip;
|
||||
struct sys_device sysdev;
|
||||
};
|
||||
|
||||
static struct jz_gpio_chip jz4740_gpio_chips[];
|
||||
|
@ -459,49 +458,47 @@ static struct jz_gpio_chip jz4740_gpio_chips[] = {
|
|||
JZ4740_GPIO_CHIP(D),
|
||||
};
|
||||
|
||||
static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
|
||||
static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
|
||||
{
|
||||
return container_of(dev, struct jz_gpio_chip, sysdev);
|
||||
}
|
||||
|
||||
static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
struct jz_gpio_chip *chip = sysdev_to_chip(dev);
|
||||
|
||||
chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
|
||||
writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
|
||||
writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
||||
}
|
||||
|
||||
static int jz4740_gpio_suspend(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
|
||||
jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_gpio_resume(struct sys_device *dev)
|
||||
static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
|
||||
{
|
||||
struct jz_gpio_chip *chip = sysdev_to_chip(dev);
|
||||
uint32_t mask = chip->suspend_mask;
|
||||
|
||||
writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
||||
writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_class jz4740_gpio_sysdev_class = {
|
||||
.name = "gpio",
|
||||
static void jz4740_gpio_resume(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
|
||||
jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
|
||||
}
|
||||
|
||||
static struct syscore_ops jz4740_gpio_syscore_ops = {
|
||||
.suspend = jz4740_gpio_suspend,
|
||||
.resume = jz4740_gpio_resume,
|
||||
};
|
||||
|
||||
static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
||||
static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
||||
{
|
||||
int ret, irq;
|
||||
|
||||
chip->sysdev.id = id;
|
||||
chip->sysdev.cls = &jz4740_gpio_sysdev_class;
|
||||
ret = sysdev_register(&chip->sysdev);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
int irq;
|
||||
|
||||
spin_lock_init(&chip->lock);
|
||||
|
||||
|
@ -519,22 +516,17 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
|||
irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init jz4740_gpio_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
|
||||
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
|
||||
|
||||
register_syscore_ops(&jz4740_gpio_syscore_ops);
|
||||
|
||||
printk(KERN_INFO "JZ4740 GPIO initialized\n");
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -19,6 +19,26 @@
|
|||
|
||||
#include <asm-generic/sections.h>
|
||||
|
||||
#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT)
|
||||
#define MCOUNT_OFFSET_INSNS 5
|
||||
#else
|
||||
#define MCOUNT_OFFSET_INSNS 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check if the address is in kernel space
|
||||
*
|
||||
* Clone core_kernel_text() from kernel/extable.c, but doesn't call
|
||||
* init_kernel_text() for Ftrace doesn't trace functions in init sections.
|
||||
*/
|
||||
static inline int in_kernel_space(unsigned long ip)
|
||||
{
|
||||
if (ip >= (unsigned long)_stext &&
|
||||
ip <= (unsigned long)_etext)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
|
||||
#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
|
||||
|
@ -54,20 +74,6 @@ static inline void ftrace_dyn_arch_init_insns(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the address is in kernel space
|
||||
*
|
||||
* Clone core_kernel_text() from kernel/extable.c, but doesn't call
|
||||
* init_kernel_text() for Ftrace doesn't trace functions in init sections.
|
||||
*/
|
||||
static inline int in_kernel_space(unsigned long ip)
|
||||
{
|
||||
if (ip >= (unsigned long)_stext &&
|
||||
ip <= (unsigned long)_etext)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
|
||||
{
|
||||
int faulted;
|
||||
|
@ -112,11 +118,6 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
|
|||
* 1: offset = 4 instructions
|
||||
*/
|
||||
|
||||
#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT)
|
||||
#define MCOUNT_OFFSET_INSNS 5
|
||||
#else
|
||||
#define MCOUNT_OFFSET_INSNS 4
|
||||
#endif
|
||||
#define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS)
|
||||
|
||||
int ftrace_make_nop(struct module *mod,
|
||||
|
|
|
@ -229,7 +229,7 @@ static void i8259A_shutdown(void)
|
|||
*/
|
||||
if (i8259A_auto_eoi >= 0) {
|
||||
outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
|
||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
|
||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -295,6 +295,7 @@ static void init_8259A(int auto_eoi)
|
|||
static struct irqaction irq2 = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct resource pic1_io_resource = {
|
||||
|
|
|
@ -349,3 +349,10 @@ SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
|
|||
return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
|
||||
dfd, pathname);
|
||||
}
|
||||
|
||||
SYSCALL_DEFINE6(32_futex, u32 __user *, uaddr, int, op, u32, val,
|
||||
struct compat_timespec __user *, utime, u32 __user *, uaddr2,
|
||||
u32, val3)
|
||||
{
|
||||
return compat_sys_futex(uaddr, op, val, utime, uaddr2, val3);
|
||||
}
|
||||
|
|
|
@ -315,7 +315,7 @@ EXPORT(sysn32_call_table)
|
|||
PTR sys_fremovexattr
|
||||
PTR sys_tkill
|
||||
PTR sys_ni_syscall
|
||||
PTR compat_sys_futex
|
||||
PTR sys_32_futex
|
||||
PTR compat_sys_sched_setaffinity /* 6195 */
|
||||
PTR compat_sys_sched_getaffinity
|
||||
PTR sys_cacheflush
|
||||
|
|
|
@ -441,7 +441,7 @@ sys_call_table:
|
|||
PTR sys_fremovexattr /* 4235 */
|
||||
PTR sys_tkill
|
||||
PTR sys_sendfile64
|
||||
PTR compat_sys_futex
|
||||
PTR sys_32_futex
|
||||
PTR compat_sys_sched_setaffinity
|
||||
PTR compat_sys_sched_getaffinity /* 4240 */
|
||||
PTR compat_sys_io_setup
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#include <linux/cache.h>
|
||||
#include <linux/irqflags.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/personality.h>
|
||||
|
@ -658,6 +659,8 @@ static void do_signal(struct pt_regs *regs)
|
|||
asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
|
||||
__u32 thread_info_flags)
|
||||
{
|
||||
local_irq_enable();
|
||||
|
||||
/* deal with pending signal delivery */
|
||||
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
|
||||
do_signal(regs);
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/bug.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
|
@ -364,21 +365,26 @@ static int regs_to_trapnr(struct pt_regs *regs)
|
|||
return (regs->cp0_cause >> 2) & 0x1f;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(die_lock);
|
||||
static DEFINE_RAW_SPINLOCK(die_lock);
|
||||
|
||||
void __noreturn die(const char *str, struct pt_regs *regs)
|
||||
{
|
||||
static int die_counter;
|
||||
int sig = SIGSEGV;
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
unsigned long dvpret = dvpe();
|
||||
unsigned long dvpret;
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
|
||||
oops_enter();
|
||||
|
||||
if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
|
||||
sig = 0;
|
||||
|
||||
console_verbose();
|
||||
spin_lock_irq(&die_lock);
|
||||
raw_spin_lock_irq(&die_lock);
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
dvpret = dvpe();
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
bust_spinlocks(1);
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
mips_mt_regdump(dvpret);
|
||||
|
@ -387,7 +393,9 @@ void __noreturn die(const char *str, struct pt_regs *regs)
|
|||
printk("%s[#%d]:\n", str, ++die_counter);
|
||||
show_registers(regs);
|
||||
add_taint(TAINT_DIE);
|
||||
spin_unlock_irq(&die_lock);
|
||||
raw_spin_unlock_irq(&die_lock);
|
||||
|
||||
oops_exit();
|
||||
|
||||
if (in_interrupt())
|
||||
panic("Fatal exception in interrupt");
|
||||
|
|
|
@ -192,7 +192,7 @@ static struct tc *get_tc(int index)
|
|||
}
|
||||
spin_unlock(&vpecontrol.tc_list_lock);
|
||||
|
||||
return NULL;
|
||||
return res;
|
||||
}
|
||||
|
||||
/* allocate a vpe and associate it with this minor (or index) */
|
||||
|
|
|
@ -123,11 +123,10 @@ void ltq_enable_irq(struct irq_data *d)
|
|||
static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_enable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
if (d->irq == ltq_eiu_irq[i]) {
|
||||
/* low level - we should really handle set_type */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
|
||||
(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
|
||||
|
@ -147,11 +146,10 @@ static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
|||
static void ltq_shutdown_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_disable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
if (d->irq == ltq_eiu_irq[i]) {
|
||||
/* disable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
|
|
|
@ -10,7 +10,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
|
|
@ -105,6 +105,7 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
static struct irqaction cascade = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -42,6 +42,7 @@ asmlinkage void mach_irq_dispatch(unsigned int pending)
|
|||
static struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init mach_init_irq(void)
|
||||
|
|
|
@ -96,12 +96,13 @@ static irqreturn_t ip6_action(int cpl, void *dev_id)
|
|||
struct irqaction ip6_irqaction = {
|
||||
.handler = ip6_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_SHARED,
|
||||
.flags = IRQF_SHARED | IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init mach_init_irq(void)
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
* Copyright (C) 2011 Wind River Systems,
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/mman.h>
|
||||
|
@ -15,12 +16,11 @@
|
|||
#include <linux/sched.h>
|
||||
|
||||
unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
|
||||
|
||||
EXPORT_SYMBOL(shm_align_mask);
|
||||
|
||||
/* gap between mmap and stack */
|
||||
#define MIN_GAP (128*1024*1024UL)
|
||||
#define MAX_GAP ((TASK_SIZE)/6*5)
|
||||
#define MAX_GAP ((TASK_SIZE)/6*5)
|
||||
|
||||
static int mmap_is_legacy(void)
|
||||
{
|
||||
|
@ -57,13 +57,13 @@ static inline unsigned long COLOUR_ALIGN_DOWN(unsigned long addr,
|
|||
return base - off;
|
||||
}
|
||||
|
||||
#define COLOUR_ALIGN(addr,pgoff) \
|
||||
#define COLOUR_ALIGN(addr, pgoff) \
|
||||
((((addr) + shm_align_mask) & ~shm_align_mask) + \
|
||||
(((pgoff) << PAGE_SHIFT) & shm_align_mask))
|
||||
|
||||
enum mmap_allocation_direction {UP, DOWN};
|
||||
|
||||
static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
||||
static unsigned long arch_get_unmapped_area_common(struct file *filp,
|
||||
unsigned long addr0, unsigned long len, unsigned long pgoff,
|
||||
unsigned long flags, enum mmap_allocation_direction dir)
|
||||
{
|
||||
|
@ -103,16 +103,16 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
|
||||
vma = find_vma(mm, addr);
|
||||
if (TASK_SIZE - len >= addr &&
|
||||
(!vma || addr + len <= vma->vm_start))
|
||||
(!vma || addr + len <= vma->vm_start))
|
||||
return addr;
|
||||
}
|
||||
|
||||
if (dir == UP) {
|
||||
addr = mm->mmap_base;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN(addr, pgoff);
|
||||
else
|
||||
addr = PAGE_ALIGN(addr);
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN(addr, pgoff);
|
||||
else
|
||||
addr = PAGE_ALIGN(addr);
|
||||
|
||||
for (vma = find_vma(current->mm, addr); ; vma = vma->vm_next) {
|
||||
/* At this point: (!vma || addr < vma->vm_end). */
|
||||
|
@ -131,28 +131,30 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
mm->free_area_cache = mm->mmap_base;
|
||||
}
|
||||
|
||||
/* either no address requested or can't fit in requested address hole */
|
||||
/*
|
||||
* either no address requested, or the mapping can't fit into
|
||||
* the requested address hole
|
||||
*/
|
||||
addr = mm->free_area_cache;
|
||||
if (do_color_align) {
|
||||
unsigned long base =
|
||||
COLOUR_ALIGN_DOWN(addr - len, pgoff);
|
||||
|
||||
if (do_color_align) {
|
||||
unsigned long base =
|
||||
COLOUR_ALIGN_DOWN(addr - len, pgoff);
|
||||
addr = base + len;
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure it can fit in the remaining address space */
|
||||
if (likely(addr > len)) {
|
||||
vma = find_vma(mm, addr - len);
|
||||
if (!vma || addr <= vma->vm_start) {
|
||||
/* remember the address as a hint for next time */
|
||||
return mm->free_area_cache = addr-len;
|
||||
/* cache the address as a hint for next time */
|
||||
return mm->free_area_cache = addr - len;
|
||||
}
|
||||
}
|
||||
|
||||
if (unlikely(mm->mmap_base < len))
|
||||
goto bottomup;
|
||||
|
||||
addr = mm->mmap_base-len;
|
||||
addr = mm->mmap_base - len;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN_DOWN(addr, pgoff);
|
||||
|
||||
|
@ -163,8 +165,8 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
* return with success:
|
||||
*/
|
||||
vma = find_vma(mm, addr);
|
||||
if (likely(!vma || addr+len <= vma->vm_start)) {
|
||||
/* remember the address as a hint for next time */
|
||||
if (likely(!vma || addr + len <= vma->vm_start)) {
|
||||
/* cache the address as a hint for next time */
|
||||
return mm->free_area_cache = addr;
|
||||
}
|
||||
|
||||
|
@ -173,7 +175,7 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
mm->cached_hole_size = vma->vm_start - addr;
|
||||
|
||||
/* try just below the current vma->vm_start */
|
||||
addr = vma->vm_start-len;
|
||||
addr = vma->vm_start - len;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN_DOWN(addr, pgoff);
|
||||
} while (likely(len < vma->vm_start));
|
||||
|
@ -201,7 +203,7 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr0,
|
||||
unsigned long len, unsigned long pgoff, unsigned long flags)
|
||||
{
|
||||
return arch_get_unmapped_area_foo(filp,
|
||||
return arch_get_unmapped_area_common(filp,
|
||||
addr0, len, pgoff, flags, UP);
|
||||
}
|
||||
|
||||
|
@ -213,7 +215,7 @@ unsigned long arch_get_unmapped_area_topdown(struct file *filp,
|
|||
unsigned long addr0, unsigned long len, unsigned long pgoff,
|
||||
unsigned long flags)
|
||||
{
|
||||
return arch_get_unmapped_area_foo(filp,
|
||||
return arch_get_unmapped_area_common(filp,
|
||||
addr0, len, pgoff, flags, DOWN);
|
||||
}
|
||||
|
||||
|
|
|
@ -1759,14 +1759,13 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
|
|||
u32 *p = handle_tlbm;
|
||||
struct uasm_label *l = labels;
|
||||
struct uasm_reloc *r = relocs;
|
||||
struct work_registers wr;
|
||||
|
||||
memset(handle_tlbm, 0, sizeof(handle_tlbm));
|
||||
memset(labels, 0, sizeof(labels));
|
||||
memset(relocs, 0, sizeof(relocs));
|
||||
|
||||
build_r3000_tlbchange_handler_head(&p, K0, K1);
|
||||
build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
|
||||
build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
|
||||
uasm_i_nop(&p); /* load delay */
|
||||
build_make_write(&p, &r, K0, K1);
|
||||
build_r3000_pte_reload_tlbwi(&p, K0, K1);
|
||||
|
@ -1963,7 +1962,8 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
|
|||
uasm_i_andi(&p, wr.r3, wr.r3, 2);
|
||||
uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
|
||||
}
|
||||
|
||||
if (PM_DEFAULT_MASK == 0)
|
||||
uasm_i_nop(&p);
|
||||
/*
|
||||
* We clobbered C0_PAGEMASK, restore it. On the other branch
|
||||
* it is restored in build_huge_tlb_write_entry.
|
||||
|
|
|
@ -350,12 +350,14 @@ unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
|
|||
|
||||
static struct irqaction i8259irq = {
|
||||
.handler = no_action,
|
||||
.name = "XT-PIC cascade"
|
||||
.name = "XT-PIC cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction corehi_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "CoreHi"
|
||||
.name = "CoreHi",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static msc_irqmap_t __initdata msc_irqmap[] = {
|
||||
|
|
|
@ -2,4 +2,4 @@ obj-y += setup.o platform.o irq.o setup.o time.o
|
|||
obj-$(CONFIG_SMP) += smp.o smpboot.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
|
||||
|
||||
EXTRA_CFLAGS += -Werror
|
||||
ccflags-y += -Werror
|
||||
|
|
|
@ -171,8 +171,13 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
|
|||
u32 temp_buffer;
|
||||
|
||||
/* set clock to 33Mhz */
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
|
||||
if (ltq_is_ar9()) {
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR);
|
||||
} else {
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
|
||||
}
|
||||
|
||||
/* external or internal clock ? */
|
||||
if (conf->clock) {
|
||||
|
|
|
@ -215,7 +215,7 @@ static int __init rc32434_pci_init(void)
|
|||
rc32434_pcibridge_init();
|
||||
|
||||
io_map_base = ioremap(rc32434_res_pci_io1.start,
|
||||
resource_size(&rcrc32434_res_pci_io1));
|
||||
resource_size(&rc32434_res_pci_io1));
|
||||
|
||||
if (!io_map_base)
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -108,12 +108,14 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
static struct irqaction cic_cascade_msp = {
|
||||
.handler = no_action,
|
||||
.name = "MSP CIC cascade"
|
||||
.name = "MSP CIC cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction per_cascade_msp = {
|
||||
.handler = no_action,
|
||||
.name = "MSP PER cascade"
|
||||
.name = "MSP PER cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -167,7 +167,7 @@ static struct irq_chip level_irq_type = {
|
|||
|
||||
static struct irqaction gic_action = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "GIC",
|
||||
};
|
||||
|
||||
|
|
|
@ -155,32 +155,32 @@ static void __irq_entry indy_buserror_irq(void)
|
|||
|
||||
static struct irqaction local0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "local0 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction local1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "local1 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction buserr = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "Bus Error",
|
||||
};
|
||||
|
||||
static struct irqaction map0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "mapable0 cascade",
|
||||
};
|
||||
|
||||
#ifdef USE_LIO3_IRQ
|
||||
static struct irqaction map1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "mapable1 cascade",
|
||||
};
|
||||
#define SGI_INTERRUPTS SGINT_END
|
||||
|
|
|
@ -359,6 +359,7 @@ void sni_rm200_init_8259A(void)
|
|||
static struct irqaction sni_rm200_irq2 = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct resource sni_rm200_pic1_resource = {
|
||||
|
|
|
@ -34,6 +34,7 @@ static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
|
|||
static struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
|
||||
|
|
|
@ -280,7 +280,7 @@ static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
|
|||
return retval;
|
||||
}
|
||||
#else
|
||||
#define srmmu_hwprobe(addr) (srmmu_swprobe(addr, 0) & SRMMU_PTE_PMASK)
|
||||
#define srmmu_hwprobe(addr) srmmu_swprobe(addr, 0)
|
||||
#endif
|
||||
|
||||
static inline int
|
||||
|
|
|
@ -230,7 +230,8 @@ static void pci_parse_of_addrs(struct platform_device *op,
|
|||
res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
|
||||
} else if (i == dev->rom_base_reg) {
|
||||
res = &dev->resource[PCI_ROM_RESOURCE];
|
||||
flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
|
||||
flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
|
||||
| IORESOURCE_SIZEALIGN;
|
||||
} else {
|
||||
printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
|
||||
continue;
|
||||
|
|
|
@ -273,10 +273,7 @@ void do_sigreturn32(struct pt_regs *regs)
|
|||
case 1: set.sig[0] = seta[0] + (((long)seta[1]) << 32);
|
||||
}
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
|
||||
segv:
|
||||
|
@ -377,10 +374,7 @@ asmlinkage void do_rt_sigreturn32(struct pt_regs *regs)
|
|||
case 1: set.sig[0] = seta.sig[0] + (((long)seta.sig[1]) << 32);
|
||||
}
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
segv:
|
||||
force_sig(SIGSEGV, current);
|
||||
|
@ -782,6 +776,7 @@ static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
|
|||
siginfo_t *info,
|
||||
sigset_t *oldset, struct pt_regs *regs)
|
||||
{
|
||||
sigset_t blocked;
|
||||
int err;
|
||||
|
||||
if (ka->sa.sa_flags & SA_SIGINFO)
|
||||
|
@ -792,12 +787,10 @@ static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
|
||||
sigorsets(&blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NOMASK))
|
||||
sigaddset(¤t->blocked,signr);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
sigaddset(&blocked, signr);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
tracehook_signal_handler(signr, info, ka, regs, 0);
|
||||
|
||||
|
@ -881,7 +874,7 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
|
|||
*/
|
||||
if (current_thread_info()->status & TS_RESTORE_SIGMASK) {
|
||||
current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
|
||||
sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -62,12 +62,13 @@ struct rt_signal_frame {
|
|||
|
||||
static int _sigpause_common(old_sigset_t set)
|
||||
{
|
||||
set &= _BLOCKABLE;
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigset_t blocked;
|
||||
|
||||
current->saved_sigmask = current->blocked;
|
||||
siginitset(¤t->blocked, set);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
|
||||
set &= _BLOCKABLE;
|
||||
siginitset(&blocked, set);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -139,10 +140,7 @@ asmlinkage void do_sigreturn(struct pt_regs *regs)
|
|||
goto segv_and_exit;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
|
||||
segv_and_exit:
|
||||
|
@ -209,10 +207,7 @@ asmlinkage void do_rt_sigreturn(struct pt_regs *regs)
|
|||
}
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
segv:
|
||||
force_sig(SIGSEGV, current);
|
||||
|
@ -470,6 +465,7 @@ static inline int
|
|||
handle_signal(unsigned long signr, struct k_sigaction *ka,
|
||||
siginfo_t *info, sigset_t *oldset, struct pt_regs *regs)
|
||||
{
|
||||
sigset_t blocked;
|
||||
int err;
|
||||
|
||||
if (ka->sa.sa_flags & SA_SIGINFO)
|
||||
|
@ -480,12 +476,10 @@ handle_signal(unsigned long signr, struct k_sigaction *ka,
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
|
||||
sigorsets(&blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NOMASK))
|
||||
sigaddset(¤t->blocked, signr);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
sigaddset(&blocked, signr);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
tracehook_signal_handler(signr, info, ka, regs, 0);
|
||||
|
||||
|
@ -581,7 +575,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
|
|||
*/
|
||||
if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
|
||||
clear_thread_flag(TIF_RESTORE_SIGMASK);
|
||||
sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -70,10 +70,7 @@ asmlinkage void sparc64_set_context(struct pt_regs *regs)
|
|||
goto do_sigsegv;
|
||||
}
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
}
|
||||
if (test_thread_flag(TIF_32BIT)) {
|
||||
pc &= 0xffffffff;
|
||||
|
@ -242,12 +239,13 @@ struct rt_signal_frame {
|
|||
|
||||
static long _sigpause_common(old_sigset_t set)
|
||||
{
|
||||
set &= _BLOCKABLE;
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigset_t blocked;
|
||||
|
||||
current->saved_sigmask = current->blocked;
|
||||
siginitset(¤t->blocked, set);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
|
||||
set &= _BLOCKABLE;
|
||||
siginitset(&blocked, set);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -327,10 +325,7 @@ void do_rt_sigreturn(struct pt_regs *regs)
|
|||
pt_regs_clear_syscall(regs);
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
segv:
|
||||
force_sig(SIGSEGV, current);
|
||||
|
@ -484,18 +479,17 @@ static inline int handle_signal(unsigned long signr, struct k_sigaction *ka,
|
|||
siginfo_t *info,
|
||||
sigset_t *oldset, struct pt_regs *regs)
|
||||
{
|
||||
sigset_t blocked;
|
||||
int err;
|
||||
|
||||
err = setup_rt_frame(ka, regs, signr, oldset,
|
||||
(ka->sa.sa_flags & SA_SIGINFO) ? info : NULL);
|
||||
if (err)
|
||||
return err;
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
|
||||
sigorsets(&blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NOMASK))
|
||||
sigaddset(¤t->blocked,signr);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
sigaddset(&blocked, signr);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
tracehook_signal_handler(signr, info, ka, regs, 0);
|
||||
|
||||
|
@ -601,7 +595,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
|
|||
*/
|
||||
if (current_thread_info()->status & TS_RESTORE_SIGMASK) {
|
||||
current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
|
||||
sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -162,7 +162,7 @@ unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr)
|
|||
printk(KERN_INFO "swprobe: padde %x\n", paddr_calc);
|
||||
if (paddr)
|
||||
*paddr = paddr_calc;
|
||||
return paddrbase;
|
||||
return pte;
|
||||
}
|
||||
|
||||
void leon_flush_icache_all(void)
|
||||
|
|
|
@ -21,7 +21,7 @@
|
|||
#include <asm/ptrace.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/irqflags.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/atomic_32.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <hv/hypervisor.h>
|
||||
#include <arch/abi.h>
|
||||
|
|
|
@ -70,7 +70,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/atomic_32.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
|
|
|
@ -56,7 +56,7 @@ DEFINE_VVAR(struct vsyscall_gtod_data, vsyscall_gtod_data) =
|
|||
.lock = __SEQLOCK_UNLOCKED(__vsyscall_gtod_data.lock),
|
||||
};
|
||||
|
||||
static enum { EMULATE, NATIVE, NONE } vsyscall_mode = EMULATE;
|
||||
static enum { EMULATE, NATIVE, NONE } vsyscall_mode = NATIVE;
|
||||
|
||||
static int __init vsyscall_setup(char *str)
|
||||
{
|
||||
|
|
|
@ -63,9 +63,8 @@ static void __init find_early_table_space(unsigned long end, int use_pse,
|
|||
#ifdef CONFIG_X86_32
|
||||
/* for fixmap */
|
||||
tables += roundup(__end_of_fixed_addresses * sizeof(pte_t), PAGE_SIZE);
|
||||
|
||||
good_end = max_pfn_mapped << PAGE_SHIFT;
|
||||
#endif
|
||||
good_end = max_pfn_mapped << PAGE_SHIFT;
|
||||
|
||||
base = memblock_find_in_range(start, good_end, tables, PAGE_SIZE);
|
||||
if (base == MEMBLOCK_ERROR)
|
||||
|
|
|
@ -43,6 +43,17 @@ static const struct dmi_system_id pci_use_crs_table[] __initconst = {
|
|||
DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
|
||||
},
|
||||
},
|
||||
/* https://bugzilla.kernel.org/show_bug.cgi?id=30552 */
|
||||
/* 2006 AMD HT/VIA system with two host bridges */
|
||||
{
|
||||
.callback = set_use_crs,
|
||||
.ident = "ASUS M2V-MX SE",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "M2V-MX SE"),
|
||||
DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
|
||||
},
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -678,38 +678,40 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
|
|||
pentry = (struct sfi_device_table_entry *)sb->pentry;
|
||||
|
||||
for (i = 0; i < num; i++, pentry++) {
|
||||
if (pentry->irq != (u8)0xff) { /* native RTE case */
|
||||
int irq = pentry->irq;
|
||||
|
||||
if (irq != (u8)0xff) { /* native RTE case */
|
||||
/* these SPI2 devices are not exposed to system as PCI
|
||||
* devices, but they have separate RTE entry in IOAPIC
|
||||
* so we have to enable them one by one here
|
||||
*/
|
||||
ioapic = mp_find_ioapic(pentry->irq);
|
||||
ioapic = mp_find_ioapic(irq);
|
||||
irq_attr.ioapic = ioapic;
|
||||
irq_attr.ioapic_pin = pentry->irq;
|
||||
irq_attr.ioapic_pin = irq;
|
||||
irq_attr.trigger = 1;
|
||||
irq_attr.polarity = 1;
|
||||
io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
|
||||
io_apic_set_pci_routing(NULL, irq, &irq_attr);
|
||||
} else
|
||||
pentry->irq = 0; /* No irq */
|
||||
irq = 0; /* No irq */
|
||||
|
||||
switch (pentry->type) {
|
||||
case SFI_DEV_TYPE_IPC:
|
||||
/* ID as IRQ is a hack that will go away */
|
||||
pdev = platform_device_alloc(pentry->name, pentry->irq);
|
||||
pdev = platform_device_alloc(pentry->name, irq);
|
||||
if (pdev == NULL) {
|
||||
pr_err("out of memory for SFI platform device '%s'.\n",
|
||||
pentry->name);
|
||||
continue;
|
||||
}
|
||||
install_irq_resource(pdev, pentry->irq);
|
||||
install_irq_resource(pdev, irq);
|
||||
pr_debug("info[%2d]: IPC bus, name = %16.16s, "
|
||||
"irq = 0x%2x\n", i, pentry->name, pentry->irq);
|
||||
"irq = 0x%2x\n", i, pentry->name, irq);
|
||||
sfi_handle_ipc_dev(pdev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_SPI:
|
||||
memset(&spi_info, 0, sizeof(spi_info));
|
||||
strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
|
||||
spi_info.irq = pentry->irq;
|
||||
spi_info.irq = irq;
|
||||
spi_info.bus_num = pentry->host_num;
|
||||
spi_info.chip_select = pentry->addr;
|
||||
spi_info.max_speed_hz = pentry->max_freq;
|
||||
|
@ -726,7 +728,7 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
|
|||
memset(&i2c_info, 0, sizeof(i2c_info));
|
||||
bus = pentry->host_num;
|
||||
strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
|
||||
i2c_info.irq = pentry->irq;
|
||||
i2c_info.irq = irq;
|
||||
i2c_info.addr = pentry->addr;
|
||||
pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
|
||||
"irq = 0x%2x, addr = 0x%x\n", i, bus,
|
||||
|
|
|
@ -67,6 +67,9 @@ static int ghash_update(struct shash_desc *desc,
|
|||
struct ghash_ctx *ctx = crypto_shash_ctx(desc->tfm);
|
||||
u8 *dst = dctx->buffer;
|
||||
|
||||
if (!ctx->gf128)
|
||||
return -ENOKEY;
|
||||
|
||||
if (dctx->bytes) {
|
||||
int n = min(srclen, dctx->bytes);
|
||||
u8 *pos = dst + (GHASH_BLOCK_SIZE - dctx->bytes);
|
||||
|
@ -119,6 +122,9 @@ static int ghash_final(struct shash_desc *desc, u8 *dst)
|
|||
struct ghash_ctx *ctx = crypto_shash_ctx(desc->tfm);
|
||||
u8 *buf = dctx->buffer;
|
||||
|
||||
if (!ctx->gf128)
|
||||
return -ENOKEY;
|
||||
|
||||
ghash_flush(ctx, dctx);
|
||||
memcpy(dst, buf, GHASH_BLOCK_SIZE);
|
||||
|
||||
|
|
|
@ -34,8 +34,8 @@ struct gpio_bank {
|
|||
u16 irq;
|
||||
u16 virtual_irq_start;
|
||||
int method;
|
||||
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
||||
u32 suspend_wakeup;
|
||||
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
||||
u32 saved_wakeup;
|
||||
#endif
|
||||
u32 non_wakeup_gpios;
|
||||
|
|
|
@ -577,6 +577,7 @@ pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
|
|||
void
|
||||
pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
|
||||
{
|
||||
*gpio_base = -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -277,7 +277,12 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
|
|||
case ATOM_ARG_FB:
|
||||
idx = U8(*ptr);
|
||||
(*ptr)++;
|
||||
val = gctx->scratch[((gctx->fb_base + idx) / 4)];
|
||||
if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
|
||||
DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
|
||||
gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
|
||||
val = 0;
|
||||
} else
|
||||
val = gctx->scratch[(gctx->fb_base / 4) + idx];
|
||||
if (print)
|
||||
DEBUG("FB[0x%02X]", idx);
|
||||
break;
|
||||
|
@ -531,7 +536,11 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
|
|||
case ATOM_ARG_FB:
|
||||
idx = U8(*ptr);
|
||||
(*ptr)++;
|
||||
gctx->scratch[((gctx->fb_base + idx) / 4)] = val;
|
||||
if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
|
||||
DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
|
||||
gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
|
||||
} else
|
||||
gctx->scratch[(gctx->fb_base / 4) + idx] = val;
|
||||
DEBUG("FB[0x%02X]", idx);
|
||||
break;
|
||||
case ATOM_ARG_PLL:
|
||||
|
@ -1370,11 +1379,13 @@ int atom_allocate_fb_scratch(struct atom_context *ctx)
|
|||
|
||||
usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
|
||||
}
|
||||
ctx->scratch_size_bytes = 0;
|
||||
if (usage_bytes == 0)
|
||||
usage_bytes = 20 * 1024;
|
||||
/* allocate some scratch memory */
|
||||
ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
|
||||
if (!ctx->scratch)
|
||||
return -ENOMEM;
|
||||
ctx->scratch_size_bytes = usage_bytes;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -137,6 +137,7 @@ struct atom_context {
|
|||
int cs_equal, cs_above;
|
||||
int io_mode;
|
||||
uint32_t *scratch;
|
||||
int scratch_size_bytes;
|
||||
};
|
||||
|
||||
extern int atom_debug;
|
||||
|
|
|
@ -466,7 +466,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
|
|||
return;
|
||||
}
|
||||
args.v2.ucEnable = enable;
|
||||
if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
|
||||
if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
|
||||
args.v2.ucEnable = ATOM_DISABLE;
|
||||
} else if (ASIC_IS_DCE3(rdev)) {
|
||||
args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
|
||||
|
|
|
@ -129,7 +129,9 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
|
|||
for (retry = 0; retry < 4; retry++) {
|
||||
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
|
||||
msg, msg_bytes, NULL, 0, delay, &ack);
|
||||
if (ret < 0)
|
||||
if (ret == -EBUSY)
|
||||
continue;
|
||||
else if (ret < 0)
|
||||
return ret;
|
||||
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
|
||||
return send_bytes;
|
||||
|
@ -160,7 +162,9 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
|
|||
for (retry = 0; retry < 4; retry++) {
|
||||
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
|
||||
msg, msg_bytes, recv, recv_bytes, delay, &ack);
|
||||
if (ret < 0)
|
||||
if (ret == -EBUSY)
|
||||
continue;
|
||||
else if (ret < 0)
|
||||
return ret;
|
||||
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
|
||||
return ret;
|
||||
|
@ -236,7 +240,9 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
|
|||
for (retry = 0; retry < 4; retry++) {
|
||||
ret = radeon_process_aux_ch(auxch,
|
||||
msg, msg_bytes, reply, reply_bytes, 0, &ack);
|
||||
if (ret < 0) {
|
||||
if (ret == -EBUSY)
|
||||
continue;
|
||||
else if (ret < 0) {
|
||||
DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -1303,23 +1303,14 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
|
|||
/* get the DPCD from the bridge */
|
||||
radeon_dp_getdpcd(radeon_connector);
|
||||
|
||||
if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
|
||||
ret = connector_status_connected;
|
||||
else {
|
||||
/* need to setup ddc on the bridge */
|
||||
if (encoder)
|
||||
radeon_atom_ext_encoder_setup_ddc(encoder);
|
||||
if (encoder) {
|
||||
/* setup ddc on the bridge */
|
||||
radeon_atom_ext_encoder_setup_ddc(encoder);
|
||||
if (radeon_ddc_probe(radeon_connector,
|
||||
radeon_connector->requires_extended_probe))
|
||||
radeon_connector->requires_extended_probe)) /* try DDC */
|
||||
ret = connector_status_connected;
|
||||
}
|
||||
|
||||
if ((ret == connector_status_disconnected) &&
|
||||
radeon_connector->dac_load_detect) {
|
||||
struct drm_encoder *encoder = radeon_best_single_encoder(connector);
|
||||
struct drm_encoder_helper_funcs *encoder_funcs;
|
||||
if (encoder) {
|
||||
encoder_funcs = encoder->helper_private;
|
||||
else if (radeon_connector->dac_load_detect) { /* try load detection */
|
||||
struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
|
||||
ret = encoder_funcs->detect(encoder, connector);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1638,7 +1638,17 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
|
|||
break;
|
||||
case 2:
|
||||
args.v2.ucCRTC = radeon_crtc->crtc_id;
|
||||
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
|
||||
if (radeon_encoder_is_dp_bridge(encoder)) {
|
||||
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
|
||||
|
||||
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
|
||||
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
|
||||
else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
|
||||
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
|
||||
else
|
||||
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
|
||||
} else
|
||||
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
|
||||
switch (radeon_encoder->encoder_id) {
|
||||
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
|
||||
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
|
||||
|
@ -1755,9 +1765,17 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
|
|||
/* DCE4/5 */
|
||||
if (ASIC_IS_DCE4(rdev)) {
|
||||
dig = radeon_encoder->enc_priv;
|
||||
if (ASIC_IS_DCE41(rdev))
|
||||
return radeon_crtc->crtc_id;
|
||||
else {
|
||||
if (ASIC_IS_DCE41(rdev)) {
|
||||
/* ontario follows DCE4 */
|
||||
if (rdev->family == CHIP_PALM) {
|
||||
if (dig->linkb)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
} else
|
||||
/* llano follows DCE3.2 */
|
||||
return radeon_crtc->crtc_id;
|
||||
} else {
|
||||
switch (radeon_encoder->encoder_id) {
|
||||
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
|
||||
if (dig->linkb)
|
||||
|
|
|
@ -321,7 +321,7 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
|
|||
struct ttm_mem_type_manager *man = &bdev->man[new_mem->mem_type];
|
||||
struct ttm_tt *ttm = bo->ttm;
|
||||
struct ttm_mem_reg *old_mem = &bo->mem;
|
||||
struct ttm_mem_reg old_copy;
|
||||
struct ttm_mem_reg old_copy = *old_mem;
|
||||
void *old_iomap;
|
||||
void *new_iomap;
|
||||
int ret;
|
||||
|
|
|
@ -390,7 +390,7 @@ temp_from_reg(u16 reg, s16 regval)
|
|||
{
|
||||
if (is_word_sized(reg))
|
||||
return LM75_TEMP_FROM_REG(regval);
|
||||
return regval * 1000;
|
||||
return ((s8)regval) * 1000;
|
||||
}
|
||||
|
||||
static inline u16
|
||||
|
@ -398,7 +398,8 @@ temp_to_reg(u16 reg, long temp)
|
|||
{
|
||||
if (is_word_sized(reg))
|
||||
return LM75_TEMP_TO_REG(temp);
|
||||
return DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000), 1000);
|
||||
return (s8)DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000),
|
||||
1000);
|
||||
}
|
||||
|
||||
/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
|
||||
|
@ -1715,7 +1716,8 @@ static void w83627ehf_device_remove_files(struct device *dev)
|
|||
}
|
||||
|
||||
/* Get the monitoring functions started */
|
||||
static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
|
||||
static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
|
||||
enum kinds kind)
|
||||
{
|
||||
int i;
|
||||
u8 tmp, diode;
|
||||
|
@ -1746,10 +1748,16 @@ static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
|
|||
w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
|
||||
|
||||
/* Get thermal sensor types */
|
||||
diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
|
||||
switch (kind) {
|
||||
case w83627ehf:
|
||||
diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
|
||||
break;
|
||||
default:
|
||||
diode = 0x70;
|
||||
}
|
||||
for (i = 0; i < 3; i++) {
|
||||
if ((tmp & (0x02 << i)))
|
||||
data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
|
||||
data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
|
||||
else
|
||||
data->temp_type[i] = 4; /* thermistor */
|
||||
}
|
||||
|
@ -2016,7 +2024,7 @@ static int __devinit w83627ehf_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* Initialize the chip */
|
||||
w83627ehf_init_device(data);
|
||||
w83627ehf_init_device(data, sio_data->kind);
|
||||
|
||||
data->vrm = vid_which_vrm();
|
||||
superio_enter(sio_data->sioreg);
|
||||
|
|
|
@ -327,7 +327,7 @@ config BLK_DEV_OPTI621
|
|||
select BLK_DEV_IDEPCI
|
||||
help
|
||||
This is a driver for the OPTi 82C621 EIDE controller.
|
||||
Please read the comments at the top of <file:drivers/ide/pci/opti621.c>.
|
||||
Please read the comments at the top of <file:drivers/ide/opti621.c>.
|
||||
|
||||
config BLK_DEV_RZ1000
|
||||
tristate "RZ1000 chipset bugfix/support"
|
||||
|
@ -365,7 +365,7 @@ config BLK_DEV_ALI15X3
|
|||
normal dual channel support.
|
||||
|
||||
Please read the comments at the top of
|
||||
<file:drivers/ide/pci/alim15x3.c>.
|
||||
<file:drivers/ide/alim15x3.c>.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
|
@ -528,7 +528,7 @@ config BLK_DEV_NS87415
|
|||
This driver adds detection and support for the NS87415 chip
|
||||
(used mainly on SPARC64 and PA-RISC machines).
|
||||
|
||||
Please read the comments at the top of <file:drivers/ide/pci/ns87415.c>.
|
||||
Please read the comments at the top of <file:drivers/ide/ns87415.c>.
|
||||
|
||||
config BLK_DEV_PDC202XX_OLD
|
||||
tristate "PROMISE PDC202{46|62|65|67} support"
|
||||
|
@ -547,7 +547,7 @@ config BLK_DEV_PDC202XX_OLD
|
|||
for more than one card.
|
||||
|
||||
Please read the comments at the top of
|
||||
<file:drivers/ide/pci/pdc202xx_old.c>.
|
||||
<file:drivers/ide/pdc202xx_old.c>.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
|
@ -593,7 +593,7 @@ config BLK_DEV_SIS5513
|
|||
ATA100: SiS635, SiS645, SiS650, SiS730, SiS735, SiS740,
|
||||
SiS745, SiS750
|
||||
|
||||
Please read the comments at the top of <file:drivers/ide/pci/sis5513.c>.
|
||||
Please read the comments at the top of <file:drivers/ide/sis5513.c>.
|
||||
|
||||
config BLK_DEV_SL82C105
|
||||
tristate "Winbond SL82c105 support"
|
||||
|
@ -616,7 +616,7 @@ config BLK_DEV_SLC90E66
|
|||
look-a-like to the PIIX4 it should be a nice addition.
|
||||
|
||||
Please read the comments at the top of
|
||||
<file:drivers/ide/pci/slc90e66.c>.
|
||||
<file:drivers/ide/slc90e66.c>.
|
||||
|
||||
config BLK_DEV_TRM290
|
||||
tristate "Tekram TRM290 chipset support"
|
||||
|
@ -625,7 +625,7 @@ config BLK_DEV_TRM290
|
|||
This driver adds support for bus master DMA transfers
|
||||
using the Tekram TRM290 PCI IDE chip. Volunteers are
|
||||
needed for further tweaking and development.
|
||||
Please read the comments at the top of <file:drivers/ide/pci/trm290.c>.
|
||||
Please read the comments at the top of <file:drivers/ide/trm290.c>.
|
||||
|
||||
config BLK_DEV_VIA82CXXX
|
||||
tristate "VIA82CXXX chipset support"
|
||||
|
@ -836,7 +836,7 @@ config BLK_DEV_ALI14XX
|
|||
of the ALI M1439/1443/1445/1487/1489 chipsets, and permits faster
|
||||
I/O speeds to be set as well.
|
||||
See the files <file:Documentation/ide/ide.txt> and
|
||||
<file:drivers/ide/legacy/ali14xx.c> for more info.
|
||||
<file:drivers/ide/ali14xx.c> for more info.
|
||||
|
||||
config BLK_DEV_DTC2278
|
||||
tristate "DTC-2278 support"
|
||||
|
@ -847,7 +847,7 @@ config BLK_DEV_DTC2278
|
|||
boot parameter. It enables support for the secondary IDE interface
|
||||
of the DTC-2278 card, and permits faster I/O speeds to be set as
|
||||
well. See the <file:Documentation/ide/ide.txt> and
|
||||
<file:drivers/ide/legacy/dtc2278.c> files for more info.
|
||||
<file:drivers/ide/dtc2278.c> files for more info.
|
||||
|
||||
config BLK_DEV_HT6560B
|
||||
tristate "Holtek HT6560B support"
|
||||
|
@ -858,7 +858,7 @@ config BLK_DEV_HT6560B
|
|||
boot parameter. It enables support for the secondary IDE interface
|
||||
of the Holtek card, and permits faster I/O speeds to be set as well.
|
||||
See the <file:Documentation/ide/ide.txt> and
|
||||
<file:drivers/ide/legacy/ht6560b.c> files for more info.
|
||||
<file:drivers/ide/ht6560b.c> files for more info.
|
||||
|
||||
config BLK_DEV_QD65XX
|
||||
tristate "QDI QD65xx support"
|
||||
|
@ -867,7 +867,7 @@ config BLK_DEV_QD65XX
|
|||
help
|
||||
This driver is enabled at runtime using the "qd65xx.probe" kernel
|
||||
boot parameter. It permits faster I/O speeds to be set. See the
|
||||
<file:Documentation/ide/ide.txt> and <file:drivers/ide/legacy/qd65xx.c>
|
||||
<file:Documentation/ide/ide.txt> and <file:drivers/ide/qd65xx.c>
|
||||
for more info.
|
||||
|
||||
config BLK_DEV_UMC8672
|
||||
|
@ -879,7 +879,7 @@ config BLK_DEV_UMC8672
|
|||
boot parameter. It enables support for the secondary IDE interface
|
||||
of the UMC-8672, and permits faster I/O speeds to be set as well.
|
||||
See the files <file:Documentation/ide/ide.txt> and
|
||||
<file:drivers/ide/legacy/umc8672.c> for more info.
|
||||
<file:drivers/ide/umc8672.c> for more info.
|
||||
|
||||
endif
|
||||
|
||||
|
|
|
@ -1124,11 +1124,8 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev,
|
|||
for (i = 0; i < 8; i++)
|
||||
__set_bit(BTN_0 + i, input_dev->keybit);
|
||||
|
||||
if (wacom_wac->features.type != WACOM_21UX2) {
|
||||
input_set_abs_params(input_dev, ABS_RX, 0, 4096, 0, 0);
|
||||
input_set_abs_params(input_dev, ABS_RY, 0, 4096, 0, 0);
|
||||
}
|
||||
|
||||
input_set_abs_params(input_dev, ABS_RX, 0, 4096, 0, 0);
|
||||
input_set_abs_params(input_dev, ABS_RY, 0, 4096, 0, 0);
|
||||
input_set_abs_params(input_dev, ABS_Z, -900, 899, 0, 0);
|
||||
|
||||
__set_bit(INPUT_PROP_DIRECT, input_dev->propbit);
|
||||
|
|
|
@ -306,6 +306,11 @@ static inline bool dma_pte_present(struct dma_pte *pte)
|
|||
return (pte->val & 3) != 0;
|
||||
}
|
||||
|
||||
static inline bool dma_pte_superpage(struct dma_pte *pte)
|
||||
{
|
||||
return (pte->val & (1 << 7));
|
||||
}
|
||||
|
||||
static inline int first_pte_in_page(struct dma_pte *pte)
|
||||
{
|
||||
return !((unsigned long)pte & ~VTD_PAGE_MASK);
|
||||
|
@ -404,6 +409,9 @@ static int dmar_forcedac;
|
|||
static int intel_iommu_strict;
|
||||
static int intel_iommu_superpage = 1;
|
||||
|
||||
int intel_iommu_gfx_mapped;
|
||||
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
|
||||
|
||||
#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
|
||||
static DEFINE_SPINLOCK(device_domain_lock);
|
||||
static LIST_HEAD(device_domain_list);
|
||||
|
@ -577,17 +585,18 @@ static void domain_update_iommu_snooping(struct dmar_domain *domain)
|
|||
|
||||
static void domain_update_iommu_superpage(struct dmar_domain *domain)
|
||||
{
|
||||
int i, mask = 0xf;
|
||||
struct dmar_drhd_unit *drhd;
|
||||
struct intel_iommu *iommu = NULL;
|
||||
int mask = 0xf;
|
||||
|
||||
if (!intel_iommu_superpage) {
|
||||
domain->iommu_superpage = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
domain->iommu_superpage = 4; /* 1TiB */
|
||||
|
||||
for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
|
||||
mask |= cap_super_page_val(g_iommus[i]->cap);
|
||||
/* set iommu_superpage to the smallest common denominator */
|
||||
for_each_active_iommu(iommu, drhd) {
|
||||
mask &= cap_super_page_val(iommu->cap);
|
||||
if (!mask) {
|
||||
break;
|
||||
}
|
||||
|
@ -730,29 +739,23 @@ static void free_context_table(struct intel_iommu *iommu)
|
|||
}
|
||||
|
||||
static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
|
||||
unsigned long pfn, int large_level)
|
||||
unsigned long pfn, int target_level)
|
||||
{
|
||||
int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
|
||||
struct dma_pte *parent, *pte = NULL;
|
||||
int level = agaw_to_level(domain->agaw);
|
||||
int offset, target_level;
|
||||
int offset;
|
||||
|
||||
BUG_ON(!domain->pgd);
|
||||
BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
|
||||
parent = domain->pgd;
|
||||
|
||||
/* Search pte */
|
||||
if (!large_level)
|
||||
target_level = 1;
|
||||
else
|
||||
target_level = large_level;
|
||||
|
||||
while (level > 0) {
|
||||
void *tmp_page;
|
||||
|
||||
offset = pfn_level_offset(pfn, level);
|
||||
pte = &parent[offset];
|
||||
if (!large_level && (pte->val & DMA_PTE_LARGE_PAGE))
|
||||
if (!target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
|
||||
break;
|
||||
if (level == target_level)
|
||||
break;
|
||||
|
@ -816,13 +819,14 @@ static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
|
|||
}
|
||||
|
||||
/* clear last level pte, a tlb flush should be followed */
|
||||
static void dma_pte_clear_range(struct dmar_domain *domain,
|
||||
static int dma_pte_clear_range(struct dmar_domain *domain,
|
||||
unsigned long start_pfn,
|
||||
unsigned long last_pfn)
|
||||
{
|
||||
int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
|
||||
unsigned int large_page = 1;
|
||||
struct dma_pte *first_pte, *pte;
|
||||
int order;
|
||||
|
||||
BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
|
||||
BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
|
||||
|
@ -846,6 +850,9 @@ static void dma_pte_clear_range(struct dmar_domain *domain,
|
|||
(void *)pte - (void *)first_pte);
|
||||
|
||||
} while (start_pfn && start_pfn <= last_pfn);
|
||||
|
||||
order = (large_page - 1) * 9;
|
||||
return order;
|
||||
}
|
||||
|
||||
/* free page table pages. last level pte should already be cleared */
|
||||
|
@ -3226,9 +3233,6 @@ static void __init init_no_remapping_devices(void)
|
|||
}
|
||||
}
|
||||
|
||||
if (dmar_map_gfx)
|
||||
return;
|
||||
|
||||
for_each_drhd_unit(drhd) {
|
||||
int i;
|
||||
if (drhd->ignored || drhd->include_all)
|
||||
|
@ -3236,18 +3240,23 @@ static void __init init_no_remapping_devices(void)
|
|||
|
||||
for (i = 0; i < drhd->devices_cnt; i++)
|
||||
if (drhd->devices[i] &&
|
||||
!IS_GFX_DEVICE(drhd->devices[i]))
|
||||
!IS_GFX_DEVICE(drhd->devices[i]))
|
||||
break;
|
||||
|
||||
if (i < drhd->devices_cnt)
|
||||
continue;
|
||||
|
||||
/* bypass IOMMU if it is just for gfx devices */
|
||||
drhd->ignored = 1;
|
||||
for (i = 0; i < drhd->devices_cnt; i++) {
|
||||
if (!drhd->devices[i])
|
||||
continue;
|
||||
drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
|
||||
/* This IOMMU has *only* gfx devices. Either bypass it or
|
||||
set the gfx_mapped flag, as appropriate */
|
||||
if (dmar_map_gfx) {
|
||||
intel_iommu_gfx_mapped = 1;
|
||||
} else {
|
||||
drhd->ignored = 1;
|
||||
for (i = 0; i < drhd->devices_cnt; i++) {
|
||||
if (!drhd->devices[i])
|
||||
continue;
|
||||
drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -3568,6 +3577,8 @@ static void domain_remove_one_dev_info(struct dmar_domain *domain,
|
|||
found = 1;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&device_domain_lock, flags);
|
||||
|
||||
if (found == 0) {
|
||||
unsigned long tmp_flags;
|
||||
spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
|
||||
|
@ -3584,8 +3595,6 @@ static void domain_remove_one_dev_info(struct dmar_domain *domain,
|
|||
spin_unlock_irqrestore(&iommu->lock, tmp_flags);
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&device_domain_lock, flags);
|
||||
}
|
||||
|
||||
static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
|
||||
|
@ -3739,6 +3748,7 @@ static int intel_iommu_domain_init(struct iommu_domain *domain)
|
|||
vm_domain_exit(dmar_domain);
|
||||
return -ENOMEM;
|
||||
}
|
||||
domain_update_iommu_cap(dmar_domain);
|
||||
domain->priv = dmar_domain;
|
||||
|
||||
return 0;
|
||||
|
@ -3864,14 +3874,15 @@ static int intel_iommu_unmap(struct iommu_domain *domain,
|
|||
{
|
||||
struct dmar_domain *dmar_domain = domain->priv;
|
||||
size_t size = PAGE_SIZE << gfp_order;
|
||||
int order;
|
||||
|
||||
dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
|
||||
order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
|
||||
(iova + size - 1) >> VTD_PAGE_SHIFT);
|
||||
|
||||
if (dmar_domain->max_addr == iova + size)
|
||||
dmar_domain->max_addr = iova;
|
||||
|
||||
return gfp_order;
|
||||
return order;
|
||||
}
|
||||
|
||||
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
|
@ -3950,7 +3961,11 @@ static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
|
|||
if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
|
||||
printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
|
||||
dmar_map_gfx = 0;
|
||||
}
|
||||
} else if (dmar_map_gfx) {
|
||||
/* we have to ensure the gfx device is idle before we flush */
|
||||
printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
|
||||
intel_iommu_strict = 1;
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
|
||||
|
|
|
@ -1698,6 +1698,8 @@ static int crypt_ctr(struct dm_target *ti, unsigned int argc, char **argv)
|
|||
}
|
||||
|
||||
ti->num_flush_requests = 1;
|
||||
ti->discard_zeroes_data_unsupported = 1;
|
||||
|
||||
return 0;
|
||||
|
||||
bad:
|
||||
|
|
|
@ -81,8 +81,10 @@ static int parse_features(struct dm_arg_set *as, struct flakey_c *fc,
|
|||
* corrupt_bio_byte <Nth_byte> <direction> <value> <bio_flags>
|
||||
*/
|
||||
if (!strcasecmp(arg_name, "corrupt_bio_byte")) {
|
||||
if (!argc)
|
||||
if (!argc) {
|
||||
ti->error = "Feature corrupt_bio_byte requires parameters";
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
r = dm_read_arg(_args + 1, as, &fc->corrupt_bio_byte, &ti->error);
|
||||
if (r)
|
||||
|
|
|
@ -628,6 +628,7 @@ void *dm_kcopyd_prepare_callback(struct dm_kcopyd_client *kc,
|
|||
job->kc = kc;
|
||||
job->fn = fn;
|
||||
job->context = context;
|
||||
job->master_job = job;
|
||||
|
||||
atomic_inc(&kc->nr_jobs);
|
||||
|
||||
|
|
|
@ -449,7 +449,7 @@ static int parse_raid_params(struct raid_set *rs, char **argv,
|
|||
rs->ti->error = "write_mostly option is only valid for RAID1";
|
||||
return -EINVAL;
|
||||
}
|
||||
if (value > rs->md.raid_disks) {
|
||||
if (value >= rs->md.raid_disks) {
|
||||
rs->ti->error = "Invalid write_mostly drive index given";
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
@ -1238,14 +1238,15 @@ static void dm_table_set_integrity(struct dm_table *t)
|
|||
return;
|
||||
|
||||
template_disk = dm_table_get_integrity_disk(t, true);
|
||||
if (!template_disk &&
|
||||
blk_integrity_is_initialized(dm_disk(t->md))) {
|
||||
if (template_disk)
|
||||
blk_integrity_register(dm_disk(t->md),
|
||||
blk_get_integrity(template_disk));
|
||||
else if (blk_integrity_is_initialized(dm_disk(t->md)))
|
||||
DMWARN("%s: device no longer has a valid integrity profile",
|
||||
dm_device_name(t->md));
|
||||
return;
|
||||
}
|
||||
blk_integrity_register(dm_disk(t->md),
|
||||
blk_get_integrity(template_disk));
|
||||
else
|
||||
DMWARN("%s: unable to establish an integrity profile",
|
||||
dm_device_name(t->md));
|
||||
}
|
||||
|
||||
static int device_flush_capable(struct dm_target *ti, struct dm_dev *dev,
|
||||
|
@ -1282,6 +1283,22 @@ static bool dm_table_supports_flush(struct dm_table *t, unsigned flush)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool dm_table_discard_zeroes_data(struct dm_table *t)
|
||||
{
|
||||
struct dm_target *ti;
|
||||
unsigned i = 0;
|
||||
|
||||
/* Ensure that all targets supports discard_zeroes_data. */
|
||||
while (i < dm_table_get_num_targets(t)) {
|
||||
ti = dm_table_get_target(t, i++);
|
||||
|
||||
if (ti->discard_zeroes_data_unsupported)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void dm_table_set_restrictions(struct dm_table *t, struct request_queue *q,
|
||||
struct queue_limits *limits)
|
||||
{
|
||||
|
@ -1304,6 +1321,9 @@ void dm_table_set_restrictions(struct dm_table *t, struct request_queue *q,
|
|||
}
|
||||
blk_queue_flush(q, flush);
|
||||
|
||||
if (!dm_table_discard_zeroes_data(t))
|
||||
q->limits.discard_zeroes_data = 0;
|
||||
|
||||
dm_table_set_integrity(t);
|
||||
|
||||
/*
|
||||
|
|
|
@ -61,6 +61,11 @@
|
|||
static void autostart_arrays(int part);
|
||||
#endif
|
||||
|
||||
/* pers_list is a list of registered personalities protected
|
||||
* by pers_lock.
|
||||
* pers_lock does extra service to protect accesses to
|
||||
* mddev->thread when the mutex cannot be held.
|
||||
*/
|
||||
static LIST_HEAD(pers_list);
|
||||
static DEFINE_SPINLOCK(pers_lock);
|
||||
|
||||
|
@ -739,7 +744,12 @@ static void mddev_unlock(mddev_t * mddev)
|
|||
} else
|
||||
mutex_unlock(&mddev->reconfig_mutex);
|
||||
|
||||
/* was we've dropped the mutex we need a spinlock to
|
||||
* make sur the thread doesn't disappear
|
||||
*/
|
||||
spin_lock(&pers_lock);
|
||||
md_wakeup_thread(mddev->thread);
|
||||
spin_unlock(&pers_lock);
|
||||
}
|
||||
|
||||
static mdk_rdev_t * find_rdev_nr(mddev_t *mddev, int nr)
|
||||
|
@ -6429,11 +6439,18 @@ mdk_thread_t *md_register_thread(void (*run) (mddev_t *), mddev_t *mddev,
|
|||
return thread;
|
||||
}
|
||||
|
||||
void md_unregister_thread(mdk_thread_t *thread)
|
||||
void md_unregister_thread(mdk_thread_t **threadp)
|
||||
{
|
||||
mdk_thread_t *thread = *threadp;
|
||||
if (!thread)
|
||||
return;
|
||||
dprintk("interrupting MD-thread pid %d\n", task_pid_nr(thread->tsk));
|
||||
/* Locking ensures that mddev_unlock does not wake_up a
|
||||
* non-existent thread
|
||||
*/
|
||||
spin_lock(&pers_lock);
|
||||
*threadp = NULL;
|
||||
spin_unlock(&pers_lock);
|
||||
|
||||
kthread_stop(thread->tsk);
|
||||
kfree(thread);
|
||||
|
@ -7340,8 +7357,7 @@ static void reap_sync_thread(mddev_t *mddev)
|
|||
mdk_rdev_t *rdev;
|
||||
|
||||
/* resync has finished, collect result */
|
||||
md_unregister_thread(mddev->sync_thread);
|
||||
mddev->sync_thread = NULL;
|
||||
md_unregister_thread(&mddev->sync_thread);
|
||||
if (!test_bit(MD_RECOVERY_INTR, &mddev->recovery) &&
|
||||
!test_bit(MD_RECOVERY_REQUESTED, &mddev->recovery)) {
|
||||
/* success...*/
|
||||
|
|
|
@ -560,7 +560,7 @@ extern int register_md_personality(struct mdk_personality *p);
|
|||
extern int unregister_md_personality(struct mdk_personality *p);
|
||||
extern mdk_thread_t * md_register_thread(void (*run) (mddev_t *mddev),
|
||||
mddev_t *mddev, const char *name);
|
||||
extern void md_unregister_thread(mdk_thread_t *thread);
|
||||
extern void md_unregister_thread(mdk_thread_t **threadp);
|
||||
extern void md_wakeup_thread(mdk_thread_t *thread);
|
||||
extern void md_check_recovery(mddev_t *mddev);
|
||||
extern void md_write_start(mddev_t *mddev, struct bio *bi);
|
||||
|
|
|
@ -514,8 +514,7 @@ static int multipath_stop (mddev_t *mddev)
|
|||
{
|
||||
multipath_conf_t *conf = mddev->private;
|
||||
|
||||
md_unregister_thread(mddev->thread);
|
||||
mddev->thread = NULL;
|
||||
md_unregister_thread(&mddev->thread);
|
||||
blk_sync_queue(mddev->queue); /* the unplug fn references 'conf'*/
|
||||
mempool_destroy(conf->pool);
|
||||
kfree(conf->multipaths);
|
||||
|
|
|
@ -2562,8 +2562,7 @@ static int stop(mddev_t *mddev)
|
|||
raise_barrier(conf);
|
||||
lower_barrier(conf);
|
||||
|
||||
md_unregister_thread(mddev->thread);
|
||||
mddev->thread = NULL;
|
||||
md_unregister_thread(&mddev->thread);
|
||||
if (conf->r1bio_pool)
|
||||
mempool_destroy(conf->r1bio_pool);
|
||||
kfree(conf->mirrors);
|
||||
|
|
|
@ -2955,7 +2955,7 @@ static int run(mddev_t *mddev)
|
|||
return 0;
|
||||
|
||||
out_free_conf:
|
||||
md_unregister_thread(mddev->thread);
|
||||
md_unregister_thread(&mddev->thread);
|
||||
if (conf->r10bio_pool)
|
||||
mempool_destroy(conf->r10bio_pool);
|
||||
safe_put_page(conf->tmppage);
|
||||
|
@ -2973,8 +2973,7 @@ static int stop(mddev_t *mddev)
|
|||
raise_barrier(conf, 0);
|
||||
lower_barrier(conf);
|
||||
|
||||
md_unregister_thread(mddev->thread);
|
||||
mddev->thread = NULL;
|
||||
md_unregister_thread(&mddev->thread);
|
||||
blk_sync_queue(mddev->queue); /* the unplug fn references 'conf'*/
|
||||
if (conf->r10bio_pool)
|
||||
mempool_destroy(conf->r10bio_pool);
|
||||
|
|
|
@ -4941,8 +4941,7 @@ static int run(mddev_t *mddev)
|
|||
|
||||
return 0;
|
||||
abort:
|
||||
md_unregister_thread(mddev->thread);
|
||||
mddev->thread = NULL;
|
||||
md_unregister_thread(&mddev->thread);
|
||||
if (conf) {
|
||||
print_raid5_conf(conf);
|
||||
free_conf(conf);
|
||||
|
@ -4956,8 +4955,7 @@ static int stop(mddev_t *mddev)
|
|||
{
|
||||
raid5_conf_t *conf = mddev->private;
|
||||
|
||||
md_unregister_thread(mddev->thread);
|
||||
mddev->thread = NULL;
|
||||
md_unregister_thread(&mddev->thread);
|
||||
if (mddev->queue)
|
||||
mddev->queue->backing_dev_info.congested_fn = NULL;
|
||||
free_conf(conf);
|
||||
|
|
|
@ -181,7 +181,7 @@ static void v4l2_device_release(struct device *cd)
|
|||
* TODO: In the long run all drivers that use v4l2_device should use the
|
||||
* v4l2_device release callback. This check will then be unnecessary.
|
||||
*/
|
||||
if (v4l2_dev->release == NULL)
|
||||
if (v4l2_dev && v4l2_dev->release == NULL)
|
||||
v4l2_dev = NULL;
|
||||
|
||||
/* Release video_device and perform other
|
||||
|
|
|
@ -239,13 +239,19 @@ void bnx2x_int_disable(struct bnx2x *bp);
|
|||
* FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
|
||||
*
|
||||
*/
|
||||
/* iSCSI L2 */
|
||||
#define BNX2X_ISCSI_ETH_CL_ID_IDX 1
|
||||
#define BNX2X_ISCSI_ETH_CID 49
|
||||
enum {
|
||||
BNX2X_ISCSI_ETH_CL_ID_IDX,
|
||||
BNX2X_FCOE_ETH_CL_ID_IDX,
|
||||
BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
|
||||
};
|
||||
|
||||
/* FCoE L2 */
|
||||
#define BNX2X_FCOE_ETH_CL_ID_IDX 2
|
||||
#define BNX2X_FCOE_ETH_CID 50
|
||||
#define BNX2X_CNIC_START_ETH_CID 48
|
||||
enum {
|
||||
/* iSCSI L2 */
|
||||
BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID,
|
||||
/* FCoE L2 */
|
||||
BNX2X_FCOE_ETH_CID,
|
||||
};
|
||||
|
||||
/** Additional rings budgeting */
|
||||
#ifdef BCM_CNIC
|
||||
|
|
|
@ -1297,7 +1297,7 @@ static inline void bnx2x_init_txdata(struct bnx2x *bp,
|
|||
static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
|
||||
{
|
||||
return bp->cnic_base_cl_id + cl_idx +
|
||||
(bp->pf_num >> 1) * NON_ETH_CONTEXT_USE;
|
||||
(bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
|
||||
}
|
||||
|
||||
static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
|
||||
|
|
|
@ -1435,6 +1435,8 @@ static rx_handler_result_t bond_handle_frame(struct sk_buff **pskb)
|
|||
struct sk_buff *skb = *pskb;
|
||||
struct slave *slave;
|
||||
struct bonding *bond;
|
||||
void (*recv_probe)(struct sk_buff *, struct bonding *,
|
||||
struct slave *);
|
||||
|
||||
skb = skb_share_check(skb, GFP_ATOMIC);
|
||||
if (unlikely(!skb))
|
||||
|
@ -1448,11 +1450,12 @@ static rx_handler_result_t bond_handle_frame(struct sk_buff **pskb)
|
|||
if (bond->params.arp_interval)
|
||||
slave->dev->last_rx = jiffies;
|
||||
|
||||
if (bond->recv_probe) {
|
||||
recv_probe = ACCESS_ONCE(bond->recv_probe);
|
||||
if (recv_probe) {
|
||||
struct sk_buff *nskb = skb_clone(skb, GFP_ATOMIC);
|
||||
|
||||
if (likely(nskb)) {
|
||||
bond->recv_probe(nskb, bond, slave);
|
||||
recv_probe(nskb, bond, slave);
|
||||
dev_kfree_skb(nskb);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -261,11 +261,13 @@ static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
void __iomem *data = ®s->tx.dsr1_0;
|
||||
u16 *payload = (u16 *)frame->data;
|
||||
|
||||
/* It is safe to write into dsr[dlc+1] */
|
||||
for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
|
||||
for (i = 0; i < frame->can_dlc / 2; i++) {
|
||||
out_be16(data, *payload++);
|
||||
data += 2 + _MSCAN_RESERVED_DSR_SIZE;
|
||||
}
|
||||
/* write remaining byte if necessary */
|
||||
if (frame->can_dlc & 1)
|
||||
out_8(data, frame->data[frame->can_dlc - 1]);
|
||||
}
|
||||
|
||||
out_8(®s->tx.dlr, frame->can_dlc);
|
||||
|
@ -330,10 +332,13 @@ static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
|
|||
void __iomem *data = ®s->rx.dsr1_0;
|
||||
u16 *payload = (u16 *)frame->data;
|
||||
|
||||
for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
|
||||
for (i = 0; i < frame->can_dlc / 2; i++) {
|
||||
*payload++ = in_be16(data);
|
||||
data += 2 + _MSCAN_RESERVED_DSR_SIZE;
|
||||
}
|
||||
/* read remaining byte if necessary */
|
||||
if (frame->can_dlc & 1)
|
||||
frame->data[frame->can_dlc - 1] = in_8(data);
|
||||
}
|
||||
|
||||
out_8(®s->canrflg, MSCAN_RXF);
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue