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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Not much happening, should have dequeued this lot earlier. One amdgpu, one nouveau and one exynos fix" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/exynos: atomic check only enabled crtc states drm/nouveau/bios/fan: hardcode the fan mode to linear drm/amdgpu: fix user fence handling
This commit is contained in:
commit
2bfd43d806
4 changed files with 48 additions and 22 deletions
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@ -1264,7 +1264,8 @@ struct amdgpu_cs_parser {
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struct ww_acquire_ctx ticket;
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/* user fence */
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struct amdgpu_user_fence uf;
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struct amdgpu_user_fence uf;
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struct amdgpu_bo_list_entry uf_entry;
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};
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struct amdgpu_job {
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@ -127,6 +127,37 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
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return 0;
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}
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static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
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struct drm_amdgpu_cs_chunk_fence *fence_data)
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{
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struct drm_gem_object *gobj;
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uint32_t handle;
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handle = fence_data->handle;
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gobj = drm_gem_object_lookup(p->adev->ddev, p->filp,
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fence_data->handle);
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if (gobj == NULL)
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return -EINVAL;
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p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
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p->uf.offset = fence_data->offset;
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if (amdgpu_ttm_tt_has_userptr(p->uf.bo->tbo.ttm)) {
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drm_gem_object_unreference_unlocked(gobj);
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return -EINVAL;
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}
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p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo);
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p->uf_entry.prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
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p->uf_entry.allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
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p->uf_entry.priority = 0;
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p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
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p->uf_entry.tv.shared = true;
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drm_gem_object_unreference_unlocked(gobj);
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return 0;
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}
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int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
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{
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union drm_amdgpu_cs *cs = data;
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@ -207,28 +238,15 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
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case AMDGPU_CHUNK_ID_FENCE:
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size = sizeof(struct drm_amdgpu_cs_chunk_fence);
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if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
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uint32_t handle;
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struct drm_gem_object *gobj;
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struct drm_amdgpu_cs_chunk_fence *fence_data;
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fence_data = (void *)p->chunks[i].kdata;
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handle = fence_data->handle;
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gobj = drm_gem_object_lookup(p->adev->ddev,
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p->filp, handle);
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if (gobj == NULL) {
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ret = -EINVAL;
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goto free_partial_kdata;
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}
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p->uf.bo = gem_to_amdgpu_bo(gobj);
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amdgpu_bo_ref(p->uf.bo);
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drm_gem_object_unreference_unlocked(gobj);
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p->uf.offset = fence_data->offset;
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} else {
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if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
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ret = -EINVAL;
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goto free_partial_kdata;
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}
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ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata);
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if (ret)
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goto free_partial_kdata;
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break;
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case AMDGPU_CHUNK_ID_DEPENDENCIES:
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@ -391,6 +409,9 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
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p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
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&p->validated);
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if (p->uf.bo)
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list_add(&p->uf_entry.tv.head, &p->validated);
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if (need_mmap_lock)
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down_read(¤t->mm->mmap_sem);
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@ -488,8 +509,8 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
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for (i = 0; i < parser->num_ibs; i++)
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amdgpu_ib_free(parser->adev, &parser->ibs[i]);
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kfree(parser->ibs);
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if (parser->uf.bo)
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amdgpu_bo_unref(&parser->uf.bo);
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amdgpu_bo_unref(&parser->uf.bo);
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amdgpu_bo_unref(&parser->uf_entry.robj);
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}
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static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
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@ -55,6 +55,9 @@ static int exynos_crtc_atomic_check(struct drm_crtc *crtc,
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{
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struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
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if (!state->enable)
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return 0;
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if (exynos_crtc->ops->atomic_check)
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return exynos_crtc->ops->atomic_check(exynos_crtc, state);
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@ -83,6 +83,7 @@ nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
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fan->type = NVBIOS_THERM_FAN_UNK;
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}
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fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
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fan->min_duty = nvbios_rd08(bios, data + 0x02);
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fan->max_duty = nvbios_rd08(bios, data + 0x03);
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