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synced 2024-08-27 19:29:37 +00:00
[MTD NAND] s3c2412 support in s3c2410.c
Add support for both the S3C2412 and S3C2412 Samsung SoCs to the increasingly mis-named s3c2410.c driver. This currently only supports SLC ECCs, and a chip on nFCE0. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
This commit is contained in:
parent
62ed948cb1
commit
2c06a08217
2 changed files with 158 additions and 44 deletions
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@ -97,6 +97,12 @@ struct s3c2410_nand_mtd {
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int scan_res;
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};
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enum s3c_cpu_type {
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TYPE_S3C2410,
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TYPE_S3C2412,
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TYPE_S3C2440,
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};
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/* overview of the s3c2410 nand state */
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struct s3c2410_nand_info {
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@ -110,9 +116,11 @@ struct s3c2410_nand_info {
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struct resource *area;
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struct clk *clk;
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void __iomem *regs;
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void __iomem *sel_reg;
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int sel_bit;
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int mtd_count;
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unsigned char is_s3c2440;
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enum s3c_cpu_type cpu_type;
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};
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/* conversion functions */
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@ -146,7 +154,7 @@ static inline int allow_clk_stop(struct s3c2410_nand_info *info)
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#define NS_IN_KHZ 1000000
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static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
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static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
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{
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int result;
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@ -170,24 +178,26 @@ static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
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/* controller setup */
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static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev)
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static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
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struct platform_device *pdev)
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{
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struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
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unsigned long clkrate = clk_get_rate(info->clk);
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int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
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int tacls, twrph0, twrph1;
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unsigned long cfg;
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unsigned long cfg = 0;
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/* calculate the timing information for the controller */
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clkrate /= 1000; /* turn clock into kHz for ease of use */
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if (plat != NULL) {
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tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4);
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twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
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twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
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tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
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twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
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twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
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} else {
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/* default timings */
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tacls = 4;
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tacls = tacls_max;
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twrph0 = 8;
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twrph1 = 8;
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}
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@ -200,20 +210,23 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_d
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dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
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tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
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if (!info->is_s3c2440) {
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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cfg = S3C2410_NFCONF_EN;
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cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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} else {
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break;
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case TYPE_S3C2440:
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case TYPE_S3C2412:
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cfg = S3C2440_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
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/* enable the controller and de-assert nFCE */
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writel(S3C2440_NFCONT_ENABLE | S3C2440_NFCONT_ENABLE,
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info->regs + S3C2440_NFCONT);
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writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
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}
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dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
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@ -229,23 +242,18 @@ static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
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struct s3c2410_nand_info *info;
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struct s3c2410_nand_mtd *nmtd;
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struct nand_chip *this = mtd->priv;
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void __iomem *reg;
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unsigned long cur;
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unsigned long bit;
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nmtd = this->priv;
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info = nmtd->info;
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bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE;
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reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF);
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if (chip != -1 && allow_clk_stop(info))
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clk_enable(info->clk);
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cur = readl(reg);
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cur = readl(info->sel_reg);
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if (chip == -1) {
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cur |= bit;
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cur |= info->sel_bit;
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} else {
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if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
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dev_err(info->device, "invalid chip %d\n", chip);
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@ -257,10 +265,10 @@ static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
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(info->platform->select_chip) (nmtd->set, chip);
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}
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cur &= ~bit;
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cur &= ~info->sel_bit;
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}
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writel(cur, reg);
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writel(cur, info->sel_reg);
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if (chip == -1 && allow_clk_stop(info))
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clk_disable(info->clk);
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@ -309,15 +317,25 @@ static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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static int s3c2410_nand_devready(struct mtd_info *mtd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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if (info->is_s3c2440)
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return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
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return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
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}
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static int s3c2440_nand_devready(struct mtd_info *mtd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
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}
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static int s3c2412_nand_devready(struct mtd_info *mtd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
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}
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/* ECC handling functions */
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc);
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@ -485,11 +503,8 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
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struct s3c2410_nand_set *set)
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{
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struct nand_chip *chip = &nmtd->chip;
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void __iomem *regs = info->regs;
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chip->IO_ADDR_R = info->regs + S3C2410_NFDATA;
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chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
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chip->cmd_ctrl = s3c2410_nand_hwcontrol;
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chip->dev_ready = s3c2410_nand_devready;
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chip->write_buf = s3c2410_nand_write_buf;
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chip->read_buf = s3c2410_nand_read_buf;
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chip->select_chip = s3c2410_nand_select_chip;
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@ -498,11 +513,37 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
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chip->options = 0;
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chip->controller = &info->controller;
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if (info->is_s3c2440) {
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chip->IO_ADDR_R = info->regs + S3C2440_NFDATA;
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chip->IO_ADDR_W = info->regs + S3C2440_NFDATA;
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chip->cmd_ctrl = s3c2440_nand_hwcontrol;
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}
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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chip->IO_ADDR_W = regs + S3C2410_NFDATA;
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info->sel_reg = regs + S3C2410_NFCONF;
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info->sel_bit = S3C2410_NFCONF_nFCE;
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chip->cmd_ctrl = s3c2410_nand_hwcontrol;
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chip->dev_ready = s3c2410_nand_devready;
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break;
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case TYPE_S3C2440:
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chip->IO_ADDR_W = regs + S3C2440_NFDATA;
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info->sel_reg = regs + S3C2440_NFCONT;
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info->sel_bit = S3C2440_NFCONT_nFCE;
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chip->cmd_ctrl = s3c2440_nand_hwcontrol;
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chip->dev_ready = s3c2440_nand_devready;
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break;
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case TYPE_S3C2412:
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chip->IO_ADDR_W = regs + S3C2440_NFDATA;
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info->sel_reg = regs + S3C2440_NFCONT;
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info->sel_bit = S3C2412_NFCONT_nFCE0;
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chip->cmd_ctrl = s3c2440_nand_hwcontrol;
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chip->dev_ready = s3c2412_nand_devready;
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if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
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dev_info(info->device, "System booted from NAND\n");
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break;
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}
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chip->IO_ADDR_R = chip->IO_ADDR_W;
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nmtd->info = info;
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nmtd->mtd.priv = chip;
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nmtd->set = set;
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if (hardware_ecc) {
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chip->ecc.correct = s3c2410_nand_correct_data;
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chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
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chip->ecc.calculate = s3c2410_nand_calculate_ecc;
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chip->ecc.correct = s3c2410_nand_correct_data;
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 512;
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chip->ecc.bytes = 3;
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chip->ecc.layout = &nand_hw_eccoob;
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if (info->is_s3c2440) {
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chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
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chip->ecc.calculate = s3c2440_nand_calculate_ecc;
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
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chip->ecc.calculate = s3c2410_nand_calculate_ecc;
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break;
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case TYPE_S3C2412:
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case TYPE_S3C2440:
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chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
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chip->ecc.calculate = s3c2440_nand_calculate_ecc;
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break;
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}
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} else {
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chip->ecc.mode = NAND_ECC_SOFT;
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@ -535,7 +584,8 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
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* nand layer to look for devices
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*/
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static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440)
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static int s3c24xx_nand_probe(struct platform_device *pdev,
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enum s3c_cpu_type cpu_type)
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{
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struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
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struct s3c2410_nand_info *info;
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info->device = &pdev->dev;
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info->platform = plat;
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info->regs = ioremap(res->start, size);
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info->is_s3c2440 = is_s3c2440;
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info->cpu_type = cpu_type;
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if (info->regs == NULL) {
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dev_err(&pdev->dev, "cannot reserve register region\n");
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static int s3c2410_nand_probe(struct platform_device *dev)
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{
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return s3c24xx_nand_probe(dev, 0);
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return s3c24xx_nand_probe(dev, TYPE_S3C2410);
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}
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static int s3c2440_nand_probe(struct platform_device *dev)
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{
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return s3c24xx_nand_probe(dev, 1);
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return s3c24xx_nand_probe(dev, TYPE_S3C2440);
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}
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static int s3c2412_nand_probe(struct platform_device *dev)
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{
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return s3c24xx_nand_probe(dev, TYPE_S3C2412);
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}
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static struct platform_driver s3c2410_nand_driver = {
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@ -727,16 +782,29 @@ static struct platform_driver s3c2440_nand_driver = {
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},
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};
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static struct platform_driver s3c2412_nand_driver = {
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.probe = s3c2412_nand_probe,
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.remove = s3c2410_nand_remove,
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.suspend = s3c24xx_nand_suspend,
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.resume = s3c24xx_nand_resume,
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.driver = {
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.name = "s3c2412-nand",
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.owner = THIS_MODULE,
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},
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};
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static int __init s3c2410_nand_init(void)
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{
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printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
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platform_driver_register(&s3c2412_nand_driver);
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platform_driver_register(&s3c2440_nand_driver);
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return platform_driver_register(&s3c2410_nand_driver);
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}
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static void __exit s3c2410_nand_exit(void)
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{
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platform_driver_unregister(&s3c2412_nand_driver);
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platform_driver_unregister(&s3c2440_nand_driver);
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platform_driver_unregister(&s3c2410_nand_driver);
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}
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@ -39,10 +39,19 @@
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#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
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#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
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#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
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#define S3C2440_NFSECC S3C2410_NFREG(0x34)
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#define S3C2440_NFSECC S3C24E10_NFREG(0x34)
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#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
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#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
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#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
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#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
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#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
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#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
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#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
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#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
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#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
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#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_512BYTE (1<<14)
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#define S3C2410_NFCONF_4STEP (1<<13)
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@ -77,5 +86,42 @@
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#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
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#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
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#define S3C2412_NFCONF_NANDBOOT (1<<31)
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#define S3C2412_NFCONF_ECCCLKCON (1<<30)
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#define S3C2412_NFCONF_ECC_MLC (1<<24)
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#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
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#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
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#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
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#define S3C2412_NFCONT_SOFTLOCK (1<<16)
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#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
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#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
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#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
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#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
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#define S3C2412_NFCONT_nFCE1 (1<<2)
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#define S3C2412_NFCONT_nFCE0 (1<<1)
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#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
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#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
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#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
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#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
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#define S3C2412_NFSTAT_nFCE1 (1<<3)
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#define S3C2412_NFSTAT_nFCE0 (1<<2)
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#define S3C2412_NFSTAT_Res1 (1<<1)
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#define S3C2412_NFSTAT_READY (1<<0)
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#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
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#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
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#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
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#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
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#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
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#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
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#define S3C2412_NFECCERR_NONE (0)
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#define S3C2412_NFECCERR_1BIT (1)
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#define S3C2412_NFECCERR_MULTIBIT (2)
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#define S3C2412_NFECCERR_ECCAREA (3)
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#endif /* __ASM_ARM_REGS_NAND */
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||||
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||||
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Loading…
Reference in a new issue